Editing Talk:intel/microarchitectures/skylake

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== documents ==

Can we collect all official Intel Skylake documents? This is seriously fucking ridiculous. There's no reason Intel should be holding back just about every architectural change they've made. It's more ridiculous we need to hunt down that shit either through test cases or through begging Intel. Can we email them directly and verify some of the ambiguous shit? --[[User:At32Hz|At32Hz]] ([[User talk:At32Hz|talk]]) 22:50, 28 April 2017 (EDT)
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	Can we collect all official Intel Skylake documents? This is seriously fucking ridiculous. There's no reason Intel should be holding back just about every architectural change they've made. It's more ridiculous we need to hunt down that shit either through test cases or through begging Intel. Can we email them directly and verify some of the ambiguous shit? --[[User:At32Hz\|At32Hz]] ([[User talk:At32Hz\|talk]]) 22:50, 28 April 2017 (EDT)		Can we collect all official Intel Skylake documents? This is seriously fucking ridiculous. There's no reason Intel should be holding back just about every architectural change they've made. It's more ridiculous we need to hunt down that shit either through test cases or through begging Intel. Can we email them directly and verify some of the ambiguous shit? --[[User:At32Hz\|At32Hz]] ([[User talk:At32Hz\|talk]]) 22:50, 28 April 2017 (EDT)
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−	: I agree Intel has not been very forthcoming regarding recent architectural improvements. I guess it's part of the reason IDF was killed next month. They simply stopped being helpful. Can we find out if the register renaming has been actually been increased? Since we've sort of reached a consensus that an actual 5th decoder was added and likewise the throughput was increased appropriately to and from the IDQ. A lot of it is simply lost if the renaming is still stack at 4 uops. This does't make much sense does it? What are we missing here? --[[User:David\|David]] ([[User talk:David\|talk]]) 19:36, 2 May 2017 (EDT)