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Report bug about L1D port sizing

In the uarch diagram, it shows 2x 32B load paths to L1D and 1x 32B store path.

The slides in here suggest that it is 2x 16B load and 1x 16B store. ("Dual 128B LD ports + 1 ST port") https://www.anandtech.com/show/12785/arm-cortex-a76-cpu-unveiled-7nm-powerhouse/3 — Preceding unsigned comment added by 104.132.0.65 (talk • contribs)

Yea, that's a typo. I've fixed it. The information in the text, under Memory subsystem, is correct though. --David (talk) 08:43, 2 May 2019 (EDT)