Page title matches

• Category:Articles with template issues
  2 members (2 subcategories, 0 files) - 19:18, 21 July 2014

Page text matches

• Category:Pages with broken file links
  [[Category:Articles with issues]]
  18 members (0 subcategories, 0 files) - 14:11, 30 November 2013
• Category:Articles with invalid parameter in template
  [[Category:Articles with template issues]]
  592 members (0 subcategories, 0 files) - 02:53, 6 July 2014
• WikiChip talk:general discussion
  .... I've commented out the affected templates but this does have to be dealt with somehow. Lastly, some languages (such as our [[mirc]] section have lost the == possibly bug with sort? ==
  27 KB (4,407 words) - 22:41, 1 January 2019
• intel/microarchitectures/bonnell
  |issues=2 ...am Intel created at their Texas Development Center in Austin in 2004 along with a new chipset ({{intel|Poulsbo|l=chipset}}) design team. The design team wa
  38 KB (5,468 words) - 20:29, 23 May 2019
• intel/microarchitectures/saltwell
  | issues = 2 * No Integer multiplier & divider (shared with FP ALU instead)
  7 KB (872 words) - 19:42, 30 November 2017
• intel/microarchitectures/silvermont
  | issues = 2 ...ploys a modular core design. Each module consists of 2 cores and 2 threads with exclusive hardware - resources are not shared. Within each module is a 1 MB
  9 KB (1,160 words) - 09:35, 25 September 2019
• intel/microarchitectures/airmont
  | issues = 2 Airmont is for the most part identical to {{intel|Silvermont}} with some higher number of execution units to the GPU in some of the higher-end
  5 KB (568 words) - 19:40, 30 November 2017
• intel/microarchitectures/broadwell (client)
  |issues=4 Broadwell is for the most part identical to {{\\|Haswell}} with several enhancements, including new instruction set extensions.
  14 KB (1,891 words) - 14:37, 6 January 2022
• intel/microarchitectures/haswell (client)
  |issues=4 ...|Ivy Bridge|Ivy}} but expands on them considerably in the execution engine with wider execution units and additional scheduler ports.
  27 KB (3,750 words) - 06:57, 18 November 2023
• intel/microarchitectures/sandy bridge (client)
  ...group and analysts brought up that it might be a bad idea to be associated with a failed Israeli political party that was eventually dissolved. The name ''Sandy Bridge'' consists of the English translation of "Gesher" with "Sandy" possible referring to the fact that silicon comes from sand.
  84 KB (13,075 words) - 00:54, 29 December 2020
• intel/microarchitectures/skylake (client)
  |issues=5 ...nstrated at the 2014 Intel Developer Forum in San Francisco on September 9 with the goals of launching in the second half of 2015.
  79 KB (11,922 words) - 06:46, 11 November 2022
• intel/microarchitectures/ice lake (client)
  Prolong delays with Intel's 10-nanometer process due to yield issues meant the terminology around that process was changed over time. Ice Lake i ...ture}} along with {{\\|Gen11}} GPU, and an improved {{intel|System Agent}} with a new display engine and I/O.
  23 KB (3,613 words) - 12:31, 20 June 2021
• Category:Pages using duplicate arguments in template calls
  [[Category:Articles with template issues]]
  8 members (0 subcategories, 0 files) - 02:06, 21 May 2016
• amd/k5
  ...ficant delays first due to early design problems and later due to problems with various [[x86]] incompatibilities. The first few models, using SSA/5, were ...ructions into simpler [[RISC]] instructions. Due to numerous manufacturing issues and design choices, K5 failed to deliver the expected performance it should
  8 KB (1,002 words) - 22:19, 17 June 2022
• WikiChip talk:general discussion/archive 1
  Per our IRC chat discussions, can we come up with a formality as to how we want to sub-organize various thing such microproce ...etting. Even for the Intel 4004, the support chips 4001-4003 have conflict with the famous [[4000 series]] which include those chips, albeit missing 4004 (
  10 KB (1,609 words) - 23:37, 27 June 2017
• amd/k6-iii
  | arch = IA-32 with MMX and 3DNow+ ...n [[L2$]] on the motherboard which ranged from 512 KB to 2MB. This changed with K6-III which added 256 KB of level 2 cache on-die. AMD branded this setup "
  9 KB (1,264 words) - 02:29, 19 January 2017
• amd/microarchitectures/k6
  ** 2-level predictor with 8192 entry branch history table ...r than 4 micro-ops are generated from the decoders, empty slots are padded with NOPs
  4 KB (578 words) - 18:57, 22 May 2019
• amd/microarchitectures/k7
  |issues=3 ...it L1$ and a unified L2$. While originally K7 had an L2$ controller on-die with the actual cache off-chip, AMD moved the L2$ on-die the following year.
  6 KB (923 words) - 16:48, 3 March 2022
• amd/microarchitectures/zen
  |issues=4 | {{amd|Raven Ridge|l=core}} || Up to 4/8 || Mobile processors with {{\\|Vega}} GPU
  79 KB (12,095 words) - 15:27, 9 June 2023
• amd/microarchitectures/zen 2
  | {{amd|Renoir|l=core}} || Up to 8/16 || Mainstream APUs with {{\\|Vega}} GPUs ...and 4 in the Zen/Zen+ microarchitecture, no calls or returns, and predicts with zero bubbles. The L1 BTB has 512 entries (256 in Zen) and creates one bubbl
  57 KB (8,701 words) - 22:11, 9 October 2022

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