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Difference between revisions of "MCST/elbrus"
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| title            = Elbrus
 
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| image            = Elbrus microprocessor.jpg
| image size        = 200px
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| developer        = MCST
 
| developer        = MCST

Latest revision as of 10:49, 10 November 2019

Elbrus
Elbrus microprocessor.jpg
Developer MCST
Type Microprocessors
Introduction 2005 (announced)
2007 (launch)
Architecture Elbrus (VLIW)
Word size 64 bit
8 octets
16 nibbles
Process 130 nm
0.13 μm
1.3e-4 mm
Package HFCBGA 900
Socket Surface mount
Succession
Elbrus-S

Elbrus (rus. Эльбрус, code designation: 1891ВМ4Я) is an universal microprocessor with the Elbrus architecture, developed by the russian company MCST in 2005.

Overview[edit]

The «Elbrus» microprocessor is a single core VLIW microprocessor providing parallel execution of 23 instructions per cycle.

Specification:

  • Built-in first level cache memory - 128 KB (64 KB for data and 64 KB for instructions)
  • Built-in overall second level cache memory - 256 KB
  • Supported type of RAM - DDR2

The average power dissipation is 6 watts. The microprocessor is intended for use in servers and computing systems[1][2].

References[edit]

Facts about "MCST/elbrus"
designerMCST +
first announced2005 +
first launched2007 +
full page nameMCST/elbrus +
instance ofmicroprocessor family +
main designerMCST +
nameElbrus +
packageHFCBGA 900 +
process130 nm (0.13 μm, 1.3e-4 mm) +
socketSurface mount +
word size64 bit (8 octets, 16 nibbles) +