From WikiChip
Difference between revisions of "650 nm lithography process"

 
(One intermediate revision by one other user not shown)
Line 25: Line 25:
 
| ? nm  || ? nm || ? nm || ? nm || ? nm
 
| ? nm  || ? nm || ? nm || ? nm || ? nm
 
|-
 
|-
| ? µm<sup>2</sup> ||  ? µm<sup>2</sup> ||  ? µm<sup>2</sup> ||  ? µm<sup>2</sup> ||  ? µm<sup>2</sup>
+
| ? µm² ||  ? µm² ||  ? µm² ||  ? µm² ||  ? µm²
 
{{scrolling table/end}}
 
{{scrolling table/end}}
  
Line 39: Line 39:
 
* Ross
 
* Ross
 
** {{ross|hyperSPARC}}
 
** {{ross|hyperSPARC}}
 +
 +
[[category:lithography]]

Latest revision as of 06:15, 20 July 2018

The 650 nanometer (650 nm) lithography process was a semiconductor manufacturing process used by some integrated circuit manufacturers in early 1990s. This process was later replaced by 500 nm and 350 nm processes.

Industry[edit]

Fab
Process Name​
1st Production​
 ​
Contacted Gate Pitch​
Interconnect Pitch (M1P)​
SRAM bit cell
Cypress IDT TI IBM Motorola
 
1992 1993 1993 1995 1995
Value Value Value Value Value
 ? nm  ? nm  ? nm  ? nm  ? nm
 ? nm  ? nm  ? nm  ? nm  ? nm
 ? µm²  ? µm²  ? µm²  ? µm²  ? µm²

650 nm Microprocessors[edit]