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5 nm lithography process
Revision as of 09:19, 1 November 2019 by David (talk | contribs) (Intel)

The 5 nanometer (5 nm or 50 Å) lithography process is a technology node semiconductor manufacturing process following the 7 nm process node. Commercial integrated circuit manufacturing using 5 nm process is set to begin sometimes around 2020.

The term "5 nm" is simply a commercial name for a generation of a certain size and its technology, and does not represent any geometry of the transistor.


First introduced by the major foundries around the 2020 timeframe, the 5-nanometer process technology is characterized by its use of FinFET transistors with fin pitches in the 20s of nanometer and densest metal pitches in the 30s of nanometers. Due to the small feature sizes, these processes make extensive use of EUV for the critical dimensions, along with quad patterning for the fins and double patterning for the rest of the metal stack. Note that Intel 7 nm process is comparable to the foundry 5-nanometer node.


In terms of raw cell-level density, the 5-nanometer node features silicon densities between 130-230 million transistors per square millimeter based on WikiChip's own analysis.

5nm densities.svg


Only three companies are currently planning or developing a 5-nanometer node: Intel, TSMC, and Samsung.

ProcessP1278 (CPU), P1279 (SoC)N5, N5P5LPP
DP (193i)
DP (193i)
Size300 mm
 Value7 nm ΔValue7 nm ΔValue7 nm Δ
FinPitch27 nm1.0x
Gate Length (Lg)8/10 nm1.0x
Contacted Gate Pitch (CPP)60 nm (HP)
54 nm (HD)
Minimum Metal Pitch (MMP)36 nm1.0x
SRAMHigh-Perf (HP)0.032 µm²1.0x
High-Density (HD)0.021 µm²0.78x0.026 µm²1.0x
Low-Voltage (LV)



Intel's 5-nanometer process node is expected to ramp around the 2023 timeframe.



TSMC started its risk production of the 5-nanometer, N5, node in March 2019 with production expected to start in the first quarter of 2020.

N5 is planned as a full node successor to the company's N7 node, featuring 1.8x improvement in logic density. The N5 node continues to use bulk silicon FinFET transistors. Leveraging their experience from 7+, 5 nm makes extensive use of EUV for more critical layers in order to reduce the multi-patterning complexity.

N5 PPA vs. N7
Speed @ iso-power Power @ iso-speed Max speed improvement
@ Vdd (eLVT)
~15% ~30% ~25%

The 5 nm node is expected to deliver a 15% improvement in performance at constant power or a 20% reduction in power at constant performance. For N5, TSMC is also offering an eLVT library that offers 25% high speed at Vdd. N5 targets both low-power mobile and high-performance compute with this node. In addition to a target density improvement of ~1.8x, TSMC has also improved the analog circuit density by ~1.2x.


As with their 7-nanometer process, TSMC will offer an optimized version of their N5 process called N5 Performance-enhanced version (N5P). This process uses the same design rules and is fully IP-compatible with N5. Through FEOL and MOL optimizations, N5P will offer 7% higher performance over N5 at iso-power or 15% lower power at iso-performance. Risk production for N5 is expected to start around the second half of 2020 with volume production starting sometimes in 2021.



Samsung 5-Nanometer Low-Power Early (5LPE) design development completed in early 2019. Unlike TSMC's 5-nanometer node, 5LPE is considered to be only a quarter node successor to the company's 7-nanometer 7LPP process, delivering 1.3x density improvement through a new standard cell library as well as new scaling boosters. Samsung 5LPE process provides different benefits depending on the migration path selected from 7LPP. Moving to a similar 7.5T library will provide 11% performance improvement through various transistor optimizations (Low-k spacer, DC enhancement, etc.). Alternatively, moving to the new 6T library provides around 33% higher density.

Speed @ iso-power Power @ iso-speed
~11% ~20%

The area benefits come from a single track reduction in the cell height, contact over the active region edge, and the use of a single diffusion break.

Samsung 5LPE provides two main libraries - 7.5T library (HD) for performance and a 6T library (UHD) for the area and power optimizations. The 7.5T library utilizes a relaxed 60 nm poly pitch with 10 diffusion lines for a cell height of 270 nanometers. This is identical to the 7LPP library. In the 7LPP process, Samsung also offered a high-density 6.75T cell library with a tighter 54 nm CPP that had 9 diffusion lines. In 5LPP, the new 6T library also utilizes the 54 nm CPP but reduces the diffusion lines to 8 for an even shorter cell height of 216 nm.


With the new 6T library, Samsung is also providing single-fin devices for ultra-low power and always-on circuits.


The 4-nanometer Low-Power Early (4LPE) process is a continuation of Samsung's 7LPP and 5LPE, inheriting the transistor and most of the ground rules from 7LPP. This is Samsung's last FinFET-based process. 4LPE features similar pitches to 5LPE but introduces slightly tighter metal pitches.

5 nm Microprocessors

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5 nm Microarchitectures

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  • WikiChip Own Research
  • TSMC Technology Symposium, 2017
  • TSMC Technology Symposium, 2018
  • TSMC Technology Symposium, 2019
  • Samsung Foundry Forum, 2019
  • Samsung, Arm TechCon, 2019
  • TSMC, Arm TechCon, 2019