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5 nm lithography process
Revision as of 16:28, 12 October 2019 by (talk) (References)

The 5 nanometer (5 nm or 50 Å) lithography process is a technology node semiconductor manufacturing process following the 7 nm process node. Commercial integrated circuit manufacturing using 5 nm process is set to begin sometimes around 2020.

The term "5 nm" is simply a commercial name for a generation of a certain size and its technology, and does not represent any geometry of the transistor.


Symbol version future.svg Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.

Process Name
1st Production
Lithography Lithography
Wafer Type
Transistor Type
Fin Pitch
Gate Length (Lg)
Contacted Gate Pitch (CPP)
Minimum Metal Pitch (MMP)
SRAM bitcell High-Perf (HP)
High-Density (HD)
Low-Voltage (LV)
DRAM bitcell eDRAM
Intel TSMC GlobalFoundries Samsung Common Platform Paper
P1278 (CPU), P1279 (SoC)        
  193 nm EUV EUV EUV
Bulk Bulk Bulk Bulk Bulk
300 mm 300 mm 300 mm 300 mm 300 mm
Value 7 nm Δ Value 7 nm Δ Value 7 nm Δ Value 7 nm Δ Value 7 nm Δ
                12 nm  
    ~44 nm 0.81x         48 nm 1.00x
    ~32 nm 0.84x            


In May of 2017, Intel's Technology and Manufacturing Group Director, Mark Bohr, confirmed that Intel was already started researching their 5 nm node as their 7nm was already in development phase.


The TSMC 5nm node uses a FinFET transistor like their 7nm process, but it makes more extensive use of EUVL. This provides a transistor density improvement of 30%-80%, and a reduction in transistor variability. The process will provide a 15% speed improvement or a 30% reduction in power compared to their standard 7nm process.

Common Platform Alliance Paper

In a joint paper by the Common Platform (IBM, GlobalFoundries, Samsung) a 5nm node was proposed at the 2017 VLSI Symposium. The paper presents a new horizontally stacked sheet gate-all-around (GAA) FET with good properties which can be a good candidate for the replacement of FinFET at the 5nm node. The paper reports transistors with an aggressive Lg of 12 nm and a contacted poly pitch of 48 nm.

ibm stacked silicon nanowire transistors.jpg

5 nm Microprocessors

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5 nm Microarchitectures

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  • TSMC, Estimated at TSMC Technology Symposium, San Jose, March 15, 2017
  • Stacked Nanosheet Gate-All-Around Transistor to Enable Scaling Beyond FinFET, 2017 Symposium on VLSI Technology / Circuits