From WikiChip
5 nm lithography process
Revision as of 12:11, 24 December 2016 by ChipIt (talk | contribs)

The 5 nanometer (5 nm) lithography process is a full node semiconductor manufacturing process following the 7 nm process node. Commercial integrated circuit manufacturing using 7 nm process is set to begin sometimes around 2021 or 2022. The term "5 nm" is simply a commercial name for a generation of a certain size and its technology, as opposed to gate length or half pitch.

Initial research

  • At the 2016 IEEE International Electron Devices Meeting (IEDM), researchers from CEA-Leti presented a paper detailing the architecture for a possible 5 nm node. The researchers presented their functional vertically stacked gate-all-around (GAA) silicon NW/NS (NanoWire/NanoSheet) MOSFETs. GAA NW transistors are a highly promising candidate to succeed FinFETs as the drive current can be optimized by vertically stacking multiple horizontal nanowires.


New text document.svg This section is empty; you can help add the missing info by editing this page.

5 nm Microprocessors

This list is incomplete; you can help by expanding it.

5 nm Microarchitectures

This list is incomplete; you can help by expanding it.