Semiconductor & Computer Engineering
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Difference between revisions of "5 nm lithography process"
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| process 1 name = P1278? (CPU), P1279? (SoC) | | process 1 name = P1278? (CPU), P1279? (SoC) | ||
| process 1 date = | | process 1 date = | ||
| − | | process 1 lith = | + | | process 1 lith = |
| process 1 immersion = | | process 1 immersion = | ||
| − | | process 1 exposure = | + | | process 1 exposure = |
| process 1 wafer type = Bulk | | process 1 wafer type = Bulk | ||
| process 1 wafer size = 300 nm | | process 1 wafer size = 300 nm | ||
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| process 4 wafer type = Bulk | | process 4 wafer type = Bulk | ||
| process 4 wafer size = 300 nm | | process 4 wafer size = 300 nm | ||
| − | | process 4 transistor = | + | | process 4 transistor = FinFET |
| process 4 volt = | | process 4 volt = | ||
| process 4 delta from = [[7 nm]] Δ | | process 4 delta from = [[7 nm]] Δ | ||
| − | | process 4 fin pitch = | + | | process 4 fin pitch = |
| − | | process 4 fin pitch Δ = | + | | process 4 fin pitch Δ = |
| − | | process 4 fin width = | + | | process 4 fin width = |
| − | | process 4 fin width Δ = | + | | process 4 fin width Δ = |
| − | | process 4 fin height = | + | | process 4 fin height = |
| − | | process 4 fin height Δ = | + | | process 4 fin height Δ = |
| process 4 gate len = | | process 4 gate len = | ||
| process 4 gate len Δ = | | process 4 gate len Δ = | ||
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=== Intel === | === Intel === | ||
In May of 2017, Intel's Technology and Manufacturing Group Director, Mark Bohr, confirmed that Intel was already started researching their 5 nm node as their 7nm was already in development phase. | In May of 2017, Intel's Technology and Manufacturing Group Director, Mark Bohr, confirmed that Intel was already started researching their 5 nm node as their 7nm was already in development phase. | ||
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== 5 nm Microprocessors== | == 5 nm Microprocessors== | ||
Revision as of 15:05, 1 June 2017
Semiconductor lithography processes technology
The 5 nanometer (5 nm or 50 Å) lithography process is a technology node semiconductor manufacturing process following the 7 nm process node. Commercial integrated circuit manufacturing using 7 nm process is set to begin sometimes around 2020.
The term "5 nm" is simply a commercial name for a generation of a certain size and its technology, and does not represent any geometry of the transistor.
Industry
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Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release. |
| Process Name | |
|---|---|
| 1st Production | |
| Lithography | Lithography |
| Immersion | |
| Exposure | |
| Wafer | Type |
| Size | |
| Transistor | Type |
| Voltage | |
| Fin | Pitch |
| Width | |
| Height | |
| Gate Length (Lg) | |
| Contacted Gate Pitch (CPP) | |
| Minimum Metal Pitch (MMP) | |
| SRAM bitcell | High-Perf (HP) |
| High-Density (HD) | |
| Low-Voltage (LV) | |
| DRAM bitcell | eDRAM |
| Intel | TSMC | GlobalFoundries | Samsung | ||||
|---|---|---|---|---|---|---|---|
| P1278? (CPU), P1279? (SoC) | |||||||
| 193 nm | EUV | EUV | |||||
| Yes | Yes | ||||||
| LELELELE | SE | SE | |||||
| Bulk | Bulk | Bulk | Bulk | ||||
| 300 nm | 300 nm | 300 nm | 300 nm | ||||
| FinFET | FinFET | FinFET | |||||
| Value | 10 nm Δ | Value | 10 nm Δ | Value | 10 nm Δ | Value | 7 nm Δ |
| ~44 nm | 0.81x | ||||||
| ~32 nm | 0.84x | ||||||
Intel
In May of 2017, Intel's Technology and Manufacturing Group Director, Mark Bohr, confirmed that Intel was already started researching their 5 nm node as their 7nm was already in development phase.
5 nm Microprocessors
This list is incomplete; you can help by expanding it.
5 nm Microarchitectures
This list is incomplete; you can help by expanding it.
References
- TSMC, Estimated at TSMC Technology Symposium, San Jose, March 15, 2017
