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Editing 5 nm lithography process

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The N5 node makes use of a number of [[density boosters]] under a marketing term called "smart hyper-scaling features" (similar to Intel). N5 introduces [[single diffusion breaks]] in order to reduce cell spacing. Additionally, TSMC added the ability to drop the gate contact over the active region (COAG). Although originally experimented with at the N7 node, [[via pillars]] are also used extensively in the N5 node. TSMC makes extensive use of [[via pillars]] in N5 due to the three-fold increase of Mx resistance.
 
The N5 node makes use of a number of [[density boosters]] under a marketing term called "smart hyper-scaling features" (similar to Intel). N5 introduces [[single diffusion breaks]] in order to reduce cell spacing. Additionally, TSMC added the ability to drop the gate contact over the active region (COAG). Although originally experimented with at the N7 node, [[via pillars]] are also used extensively in the N5 node. TSMC makes extensive use of [[via pillars]] in N5 due to the three-fold increase of Mx resistance.
 
===== SRAM =====
 
TWo [[6T]] [[SRAM]] [[bitcells]] were disclosed by TSMC. The high-performance cell is 0.025 µm² while the high-density cell is 0.021 µm². Assuming a ballpark assist circuit overhead of around 30%, the high-density cells yields an estimate of ~32 Mib/mm² of cache. This an increase of 30% from [[N7]] which is around 24.7 Mib/mm². At ISSCC 2020, TSMC presented a test shuttle with 135 Mib of HD SRAM and additional IPs. Their reported density for the HD cells is similar to our estimates.
 
 
{| class="wikitable collapsible collapsed tc1"
 
|-
 
! colspan="2" | N5 Shuttle Test Chip
 
|-
 
| colspan="2" | [[File:n5 shuttle.jpg|300px]]
 
|-
 
| Technology || 5nm HK-MG FinFET
 
|-
 
| Supply voltage || Core: 0.75V<br>IO: 1.2V
 
|-
 
| Bit cell size || 0.021 μm²
 
|-
 
| SRAM macro configuration || 1024x144 MUX4<br>256 bits/BL,<br>288 bits/WL
 
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| SRAM capacity || 135Mb
 
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| Test Features || Column Redundancy<br>Programmable E-fuse
 
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| [[Die size]] || 10mm x 7.98mm = 79.8mm2
 
|}
 
  
 
==== N5P ====
 
==== N5P ====

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