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Editing 5 nm lithography process

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[[File:n5-hmc-fin.jpg|190px|right|thumb|N5 HMC FinFet Device (IEDM 2019)]]
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[[File:n5-hmc-fin.jpg|200px|right|thumb|N5 HMC FinFet Device (IEDM 2019)]]
 
[[File:n5-channel-stress.png|200px|right|thumb|Diffraction pattern for the fully-strained HMC lattice (IEDM 2019)]]
 
[[File:n5-channel-stress.png|200px|right|thumb|Diffraction pattern for the fully-strained HMC lattice (IEDM 2019)]]
In order to improve the drive current, TSMC introduced a [[high-mobility channel]] (HMC) for its 5-nanometer [[FinFET devices]]. We believe TSMC is employing a SiGe channel for the pMOS devices. It has been suggested that the channel has 37% Ge composition. TSMC says that the HMC delivers 18% performance gain versus equivalent Si finFETs.
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In order to improve the drive current, TSMC introduced a [[high-mobility channel]] (HMC) for its 5-nanometer [[FinFET devices]]. We believe TSMC is employing a SiGe channel for the pMOS devices. It has been suggested that the channel has 37% Ge composition. TSMC says that the HMC delivers 18% performance gain versus equivalent Si finFETs. A TEM of the full-strained HMC lattice is shown on the right. Despite aggressively tighter pitches, TSMC says metal lines RC and via resistance have been kept relatively similar to N7. TSMC says this was achieved by "using EUV patterning, innovative scaled barrier/liner, ESL/ELK dielectrics, and Cu reflow." The improvements meant the interconnect RC did not worsen relative to N7 as N7 did relative to N16.
 
 
[[File:N5 mx rc and vx rc.png|right|thumb|200px|Tightest pitch Mx RC and Vx RC on 5nm was kept at similar levels to N7.]]
 
Despite aggressively tighter pitches, TSMC says metal lines RC and via resistance have been kept relatively similar to N7. TSMC says this was achieved by "using EUV patterning, innovative scaled barrier/liner, ESL/ELK dielectrics, and Cu reflow." The improvements meant the interconnect RC did not worsen relative to N7 as N7 did relative to N16.
 
  
 
The 5 nm node is expected to deliver a 15% improvement in performance at [[iso-power|constant power]] or a 20% reduction in power at [[iso-performance|constant performance]]. In addition to the ultra-LVT (uLVT) that was offered with [[N7]], there is a new extreme-LVT (eLVT) which can push that 15% up to 25% higher speed at Vdd. Additionally, compared to the standard N5 cells, the HP cell variants can push that performance by another 10% at the cost of density.
 
The 5 nm node is expected to deliver a 15% improvement in performance at [[iso-power|constant power]] or a 20% reduction in power at [[iso-performance|constant performance]]. In addition to the ultra-LVT (uLVT) that was offered with [[N7]], there is a new extreme-LVT (eLVT) which can push that 15% up to 25% higher speed at Vdd. Additionally, compared to the standard N5 cells, the HP cell variants can push that performance by another 10% at the cost of density.

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