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Editing 5 nm lithography process
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First introduced by the major foundries around the [[2020]] timeframe, the 5-nanometer [[process technology]] is characterized by its use of [[FinFET]] transistors with fin pitches in the 20s of nanometer and densest metal pitches in the 30s of nanometers. Due to the small feature sizes, these processes make extensive use of EUV for the critical dimensions, along with quad patterning for the fins and double patterning for the rest of the metal stack. Note that Intel [[7 nm process]] is comparable to the foundry 5-nanometer node. | First introduced by the major foundries around the [[2020]] timeframe, the 5-nanometer [[process technology]] is characterized by its use of [[FinFET]] transistors with fin pitches in the 20s of nanometer and densest metal pitches in the 30s of nanometers. Due to the small feature sizes, these processes make extensive use of EUV for the critical dimensions, along with quad patterning for the fins and double patterning for the rest of the metal stack. Note that Intel [[7 nm process]] is comparable to the foundry 5-nanometer node. | ||
− | === | + | === Densities === |
In terms of raw cell-level density, the 5-nanometer node features silicon densities between 130-230 million [[transistors per square millimeter]] based on WikiChip's own analysis. | In terms of raw cell-level density, the 5-nanometer node features silicon densities between 130-230 million [[transistors per square millimeter]] based on WikiChip's own analysis. | ||