Semiconductor & Computer Engineering
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Editing 5 µm lithography process
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== Industry == | == Industry == | ||
| − | HP's ''NMOS II'' was a second generation nMOD process which was a shrink of their previous generation [[7 µm]] nMOS also developed by [[HP]]'s Loveland Division. The shrink was done in the hope they could double the speed while doubling density. Loveland went on on to create a third and final process, the ''NMOS III'' using a [[1.5 µm process]]. While they succeeded in doubling the density and more than ten-folding the speed, the complexity of the chip still required them to fabricate it on 3 | + | HP's ''NMOS II'' process as the name implied was a second generation nMOD process which was a shrink of their previous generation [[7 µm]] nMOS also developed by [[HP]]'s Loveland Division. The shrink was done in the hope they could double the speed while doubling density. Loveland went on on to create a third and final process, the ''NMOS III'' using a [[1.5 µm process]]. While they succeeded in doubling the density and more than ten-folding the speed, the complexity of the chip still required them to fabricate it on 3 seperate dies and package them together. |
| − | + | {{scrolling table/top|style=text-align: right; | first=Fab | |
| − | {{ | + | |Process Name |
| − | + | |1st Production | |
| − | + | |Contacted Gate Pitch | |
| − | + | |Interconnect Pitch | |
| − | + | |Metal Layers | |
| − | + | |Technology | |
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}} | }} | ||
| + | {{scrolling table/mid}} | ||
| + | |- | ||
| + | ! [[HP]] | ||
| + | |- style="text-align: center;" | ||
| + | | NMOS II | ||
| + | |- style="text-align: center;" | ||
| + | | 1973 | ||
| + | |- | ||
| + | | ? nm | ||
| + | |- | ||
| + | | ? nm | ||
| + | |- | ||
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| + | |- | ||
| + | | nMOS | ||
| + | |- | ||
| + | | 51 mm | ||
| + | {{scrolling table/end}} | ||
== 5µm Microprocessors == | == 5µm Microprocessors == | ||
