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Difference between revisions of "45 nm lithography process"

(Industry)
(Industry: cleanup)
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|-
 
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| Metal 9 || 30.5 µm || 7 µm || 0.4
 
| Metal 9 || 30.5 µm || 7 µm || 0.4
|}
 
 
=== TSMC ===
 
{| class="wikitable"
 
|-
 
| || Measurement
 
|-
 
| Contacted Gate Pitch || 162 nm
 
|-
 
| Interconnect Pitch (M1P) || ? nm
 
|-
 
| [[SRAM]] bit cell || 0.242 µm<sup>2</sup>
 
|}
 
 
=== Crolles2 Alliance ===
 
{| class="wikitable"
 
|-
 
| || Measurement
 
|-
 
| Contacted Gate Pitch || 140 nm
 
|-
 
| Interconnect Pitch (M1P) || ? nm
 
|-
 
| [[SRAM]] bit cell || 0.250 µm<sup>2</sup>
 
 
|}
 
|}
  

Revision as of 04:59, 24 April 2016

The 45 nm lithography process is a full node semiconductor manufacturing process following the 55 nm process stopgap. Commercial integrated circuit manufacturing using 45 nm process began in 2007. This technology was superseded by the 40 nm process (HN) / 32 nm process (FN) in 2010.

Industry

Fab
Type​
 ​
Contacted Gate Pitch​
Interconnect Pitch (M1P)​
SRAM bit cell (HD)​
SRAM bit cell (LP)
Intel Fujitsu TI Toshiba / Sony / NEC IBM / Toshiba / Sony / AMD
Bulk PDSOI
Value 65 nm Δ Value 65 nm Δ Value 65 nm Δ Value 65 nm Δ Value 65 nm Δ
180 nm 0.82x 190 nm  ?x  ? nm  ?x 180 nm  ?x 190 nm 0.76x
160 nm 0.76x  ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x
0.346 µm2 0.61x 0.225 µm2  ?x 0.255 µm2  ?x 0.248 µm2  ?x 0.370 µm2 0.57x
 

Design Rules

45 nm Microprocessors

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45 nm System on Chips

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45 nm Microarchitectures

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