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Difference between revisions of "45 nm lithography process"

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| [[SRAM]] bit cell || 0.242 µm<sup>2</sup>
 
| [[SRAM]] bit cell || 0.242 µm<sup>2</sup>
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=== Crolles2 Alliance ===
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{| class="wikitable"
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| Contacted Gate Pitch || 140 nm
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| Interconnect Pitch (M1P) || ? nm
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| [[SRAM]] bit cell || 0.250 µm<sup>2</sup>
 
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Revision as of 00:15, 24 April 2016

The 45 nm lithography process is a full node semiconductor manufacturing process following the 55 nm process stopgap. Commercial integrated circuit manufacturing using 45 nm process began in 2007. This technology was superseded by the 40 nm process (HN) / 32 nm process (FN) in 2010.

Industry

Intel

Measurement Scaling from 65 nm
Contacted Gate Pitch 180 nm 0.82x
Interconnect Pitch (M1P) 160 nm 0.76x
SRAM bit cell 0.346 µm2 0.61x
Design Rules
Layer Pitch Thick Aspect Ratio
Isolation 200 nm 200 nm -
Contacted Gate 180 nm 60 nm --
Metal 1 160 nm 144 nm 1.8
Metal 2 160 nm 144 nm 1.8
Metal 3 160 nm 144 nm 1.8
Metal 4 240 nm 216 nm 1.8
Metal 5 280 nm 252 nm 1.8
Metal 6 360 nm 324 nm 1.8
Metal 7 560 nm 504 nm 1.7
Metal 8 810 nm 720 nm 1.8
Metal 9 30.5 µm 7 µm 0.4

TSMC

Measurement
Contacted Gate Pitch 162 nm
Interconnect Pitch (M1P)  ? nm
SRAM bit cell 0.242 µm2

Crolles2 Alliance

Measurement
Contacted Gate Pitch 140 nm
Interconnect Pitch (M1P)  ? nm
SRAM bit cell 0.250 µm2

45 nm Microprocessors

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45 nm System on Chips

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45 nm Microarchitectures

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