From WikiChip
Difference between revisions of "40 nm lithography process"

(→‎Industry)
(10 intermediate revisions by 6 users not shown)
Line 1: Line 1:
 
{{lithography processes}}
 
{{lithography processes}}
−
The '''40 nm lithography process''' is a [[technology node#half node|half-node]] semiconductor manufacturing process used as a stopgap between the [[45 nm lithography process|45 nm]] and [[32 nm lithography process|32 nm]] processes. Commercial [[integrated circuit]] manufacturing using 40 nm process began in 2008 by leading semiconductor companies such as [[TSMC]]. This technology superseded by commercial [[32 nm lithography process|32 nm process]] by 2010.
+
The '''40 nanometer (40 nm) lithography process''' is a [[technology node#half node|half-node]] semiconductor manufacturing process used as a stopgap between the [[45 nm lithography process|45 nm]] and [[32 nm lithography process|32 nm]] processes. Commercial [[integrated circuit]] manufacturing using 40 nm process began in 2008 by leading semiconductor companies such as [[TSMC]]. This technology superseded by commercial [[32 nm lithography process|32 nm process]] by 2010.
  
 
== Industry ==
 
== Industry ==
  
 
{{scrolling table/top|style=text-align: right; | first=Fab
 
{{scrolling table/top|style=text-align: right; | first=Fab
 +
|Wafer
 +
|Metal Layers
 +
|1st Production
 
  | 
 
  | 
 
  |Contacted Gate Pitch
 
  |Contacted Gate Pitch
Line 13: Line 16:
 
|-
 
|-
 
! colspan="2" | [[TSMC]] !! colspan="2" | [[Samsung]] !! colspan="2" | [[Toshiba]] / [[NEC]] !! colspan="2" | Crolles2 Alliance
 
! colspan="2" | [[TSMC]] !! colspan="2" | [[Samsung]] !! colspan="2" | [[Toshiba]] / [[NEC]] !! colspan="2" | Crolles2 Alliance
 +
|- style="text-align: center;"
 +
| colspan="8" | 300mm
 +
|- style="text-align: center;"
 +
| 9 || || || || || || ||
 +
|- style="text-align: center;"
 +
| 4Q 2008 || || || || || || ||
 
|-
 
|-
 
! Value !! [[65 nm]] Δ !! Value !! [[65 nm]] Δ !! Value !! [[65 nm]] Δ !! Value !! [[65 nm]] Δ
 
! Value !! [[65 nm]] Δ !! Value !! [[65 nm]] Δ !! Value !! [[65 nm]] Δ !! Value !! [[65 nm]] Δ
Line 18: Line 27:
 
| 162 nm || 1.01x || 129 nm || 0.65x || 168 nm || 0.67x || 140 nm || ?x
 
| 162 nm || 1.01x || 129 nm || 0.65x || 168 nm || 0.67x || 140 nm || ?x
 
|-
 
|-
−
| 120 nm || ?x || 117 nm || 0.65x || ? nm || ?x || ? nm || ?x
+
| 120 nm || 0.67x || 117 nm || 0.65x || ? nm || ?x || ? nm || ?x
 
|-
 
|-
 
| 0.242 µm<sup>2</sup> || 0.46x || ? µm<sup>2</sup> || ?x || 0.195 µm<sup>2</sup> || 0.33x || 0.250 µm<sup>2</sup> || ?x
 
| 0.242 µm<sup>2</sup> || 0.46x || ? µm<sup>2</sup> || ?x || 0.195 µm<sup>2</sup> || 0.33x || 0.250 µm<sup>2</sup> || ?x
Line 24: Line 33:
  
 
== 40 nm Microprocessors ==
 
== 40 nm Microprocessors ==
 +
* HiSilicon
 +
** {{hisil|K3}}
 +
* PEZY
 +
** {{pezy|PEZY-1}}
 +
* Renesas
 +
** {{renesas|R-Car}}
 
{{expand list}}
 
{{expand list}}
−
== 40 nm System on Chips ==
+
 
−
{{expand list}}
+
[[category:lithography]]

Revision as of 05:51, 20 July 2018

basic wafer drawing.svg Semiconductor lithography processes technology
v · d · e

The 40 nanometer (40 nm) lithography process is a half-node semiconductor manufacturing process used as a stopgap between the 45 nm and 32 nm processes. Commercial integrated circuit manufacturing using 40 nm process began in 2008 by leading semiconductor companies such as TSMC. This technology superseded by commercial 32 nm process by 2010.

Industry

Fab
Wafer​
Metal Layers​
1st Production​
 ​
Contacted Gate Pitch​
Interconnect Pitch (M1P)​
SRAM bit cell
TSMC Samsung Toshiba / NEC Crolles2 Alliance
300mm
9
4Q 2008
Value 65 nm Δ Value 65 nm Δ Value 65 nm Δ Value 65 nm Δ
162 nm 1.01x 129 nm 0.65x 168 nm 0.67x 140 nm  ?x
120 nm 0.67x 117 nm 0.65x  ? nm  ?x  ? nm  ?x
0.242 µm2 0.46x  ? µm2  ?x 0.195 µm2 0.33x 0.250 µm2  ?x

40 nm Microprocessors

This list is incomplete; you can help by expanding it.

Retrieved from "https://en.wikichip.org/w/index.php?title=40_nm_lithography_process&oldid=80628"