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{{lithography processes}}
 
{{lithography processes}}
The '''3.5 nanometer (3.5 nm) lithography process''' is a [[technology node|full node]] semiconductor manufacturing process following the [[5 nm lithography process|5 nm process]] node. Commercial [[integrated circuit]] manufacturing using 3.5 nm process is set to begin sometimes around 2024 or 2025. The term "3.5 nm" is simply a commercial name for a generation of a certain size and its technology, as opposed to [[technology node|gate length or half pitch]].
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The '''3 nanometer (3 nm or 30 Å) lithography process''' is a [[technology node]] semiconductor manufacturing process following the [[5 nm lithography process|5 nm process]] node. Commercial [[integrated circuit]] manufacturing using 3 nm process is set to begin some time around 2023.
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The term "3 nm" is simply a commercial name for a generation of a certain size and its technology, and '''does not''' represent any geometry of the transistor.
  
 
== Industry ==
 
== Industry ==
{{empty section}}
 
  
== 3.5 nm Microprocessors==
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{{future information}}
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{{finfet nodes comp
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<!-- Intel -->
 +
| process 1 fab          = [[Intel]]
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| process 1 name        = P1280? (CPU), P1281? (SoC)
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| process 1 date        = &nbsp;
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| process 1 lith        = EUV
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| process 1 immersion    = &nbsp;
 +
| process 1 exposure    = SE
 +
| process 1 wafer type  = Bulk
 +
| process 1 wafer size  = 300 mm
 +
| process 1 transistor  = &nbsp;
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| process 1 volt        = &nbsp;
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| process 1 delta from  = [[5 nm]] Δ
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| process 1 fin pitch    = &nbsp;
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| process 1 fin pitch Δ  = &nbsp;
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| process 1 fin width    = &nbsp;
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| process 1 fin width Δ  = &nbsp;
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| process 1 fin height  = &nbsp;
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| process 1 fin height Δ = &nbsp;
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| process 1 gate len    = &nbsp;
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| process 1 gate len Δ  = &nbsp;
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| process 1 cpp          = &nbsp;
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| process 1 cpp Δ        = &nbsp;
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| process 1 mmp          = &nbsp;
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| process 1 mmp Δ        = &nbsp;
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| process 1 sram hp      = &nbsp;
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| process 1 sram hp Δ    = &nbsp;
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| process 1 sram hd      = &nbsp;
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| process 1 sram hd Δ    = &nbsp;
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| process 1 sram lv      = &nbsp;
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| process 1 sram lv Δ    = &nbsp;
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| process 1 dram        = &nbsp;
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| process 1 dram Δ      = &nbsp;
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<!-- TSMC -->
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| process 2 fab          = [[TSMC]]
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| process 2 name        = &nbsp;
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| process 2 date        = &nbsp;
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| process 2 lith        = EUV
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| process 2 immersion    = &nbsp;
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| process 2 exposure    = SE
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| process 2 wafer type  = Bulk
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| process 2 wafer size  = 300 mm
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| process 2 transistor  = FinFET
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| process 2 volt        = &nbsp;
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| process 2 delta from  = [[5 nm]] Δ
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| process 2 fin pitch    = &nbsp;
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| process 2 fin pitch Δ  = &nbsp;
 +
| process 2 fin width    = &nbsp;
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| process 2 fin width Δ  = &nbsp;
 +
| process 2 fin height  = &nbsp;
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| process 2 fin height Δ = &nbsp;
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| process 2 gate len    = &nbsp;
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| process 2 gate len Δ  = &nbsp;
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| process 2 cpp          = &nbsp;
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| process 2 cpp Δ        = &nbsp;
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| process 2 mmp          = &nbsp;
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| process 2 mmp Δ        = &nbsp;
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| process 2 sram hp      = &nbsp;
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| process 2 sram hp Δ    = &nbsp;
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| process 2 sram hd      = &nbsp;
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| process 2 sram hd Δ    = &nbsp;
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| process 2 sram lv      = &nbsp;
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| process 2 sram lv Δ    = &nbsp;
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| process 2 dram        = &nbsp;
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| process 2 dram Δ      = &nbsp;
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<!-- Samsung -->
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| process 4 fab          = [[Samsung]]
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| process 4 name        = 3GAE<info>3nm Gate All Around Early</info>, 3GAP<info>3nm Gate All Around Plus</info>
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| process 4 date        = &nbsp;
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| process 4 lith        = EUV
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| process 4 immersion    = &nbsp;
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| process 4 exposure    = SE
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| process 4 wafer type  = Bulk
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| process 4 wafer size  = 300 mm
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| process 4 transistor  = GAA
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| process 4 volt        = &nbsp;
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| process 4 delta from  = [[5 nm]] Δ
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| process 4 fin pitch    = -
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| process 4 fin pitch Δ  =
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| process 4 fin width    =
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| process 4 fin width Δ  =
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| process 4 fin height  =
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| process 4 fin height Δ =
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| process 4 gate len    = &nbsp;
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| process 4 gate len Δ  = &nbsp;
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| process 4 cpp          = &nbsp;
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| process 4 cpp Δ        = &nbsp;
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| process 4 mmp          = &nbsp;
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| process 4 mmp Δ        = &nbsp;
 +
| process 4 sram hp      = &nbsp;
 +
| process 4 sram hp Δ    = &nbsp;
 +
| process 4 sram hd      = &nbsp;
 +
| process 4 sram hd Δ    = &nbsp;
 +
| process 4 sram lv      = &nbsp;
 +
| process 4 sram lv Δ    = &nbsp;
 +
| process 4 dram        = &nbsp;
 +
| process 4 dram Δ      = &nbsp;
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}}
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=== Samsung ===
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On May 24 2017 Samsung announced they will be switching to a transistor they call ''Multi-Bridge-Channel FET'' (''MBCFET''), an extension of a  [[Gate-all-around]] (GAA) FET. This is planned for somewhere after the 5nm node but the exact timeline or specification is currently unknown.
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== 3 nm Microprocessors==
 
{{expand list}}
 
{{expand list}}
  
== 3.5 nm Microarchitectures==
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== 3 nm Microarchitectures==
 
{{expand list}}
 
{{expand list}}
  
[[Category:Lithography]]
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== References ==
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* Kinam Kim, President of Semiconductor Business, announced MBCFET for the node after [[5 nm]], May 24, 2017
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[[category:lithography]]

Revision as of 18:48, 26 January 2021

The 3 nanometer (3 nm or 30 Å) lithography process is a technology node semiconductor manufacturing process following the 5 nm process node. Commercial integrated circuit manufacturing using 3 nm process is set to begin some time around 2023.

The term "3 nm" is simply a commercial name for a generation of a certain size and its technology, and does not represent any geometry of the transistor.

Industry

Symbol version future.svg Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.


 
Process Name
1st Production
Lithography Lithography
Immersion
Exposure
Wafer Type
Size
Transistor Type
Voltage
 
Fin Pitch
Width
Height
Gate Length (Lg)
Contacted Gate Pitch (CPP)
Minimum Metal Pitch (MMP)
SRAM bitcell High-Perf (HP)
High-Density (HD)
Low-Voltage (LV)
DRAM bitcell eDRAM
Intel TSMC Samsung
P1280? (CPU), P1281? (SoC)   3GAE
3nm Gate All Around Early
, 3GAP
3nm Gate All Around Plus
     
EUV EUV EUV
     
SE SE SE
Bulk Bulk Bulk
300 mm 300 mm 300 mm
  FinFET GAA
     
Value 5 nm Δ Value 5 nm Δ Value 5 nm Δ
        N/A
       
       
           
           
           
           
           
           
           

Samsung

On May 24 2017 Samsung announced they will be switching to a transistor they call Multi-Bridge-Channel FET (MBCFET), an extension of a Gate-all-around (GAA) FET. This is planned for somewhere after the 5nm node but the exact timeline or specification is currently unknown.

3 nm Microprocessors

This list is incomplete; you can help by expanding it.

3 nm Microarchitectures

This list is incomplete; you can help by expanding it.

References

  • Kinam Kim, President of Semiconductor Business, announced MBCFET for the node after 5 nm, May 24, 2017