Editing 3 nm lithography process

{{lithography processes}}
The '''3 nanometer (3 nm or 30 Å) lithography process''' is a [[technology node]] semiconductor manufacturing process following the [[5 nm lithography process|5 nm process]] node. Commercial [[integrated circuit]] manufacturing using 3 nm process is set to begin some time around 2023.

The term "3 nm" is simply a commercial name for a generation of a certain size and its technology, and '''does not''' represent any geometry of a transistor.

== Industry ==

{{future information}}

{{finfet nodes comp
<!-- Intel -->
 | process 1 fab          = [[Intel]]
 | process 1 name         = P1278 (CPU), P1279? (SoC)
 | process 1 date         = 2H 2023
 | process 1 lith         = EUV
 | process 1 immersion    = &nbsp;
 | process 1 exposure     = SE
 | process 1 wafer type   = Bulk
 | process 1 wafer size   = 300 mm
 | process 1 transistor   = FinFET
 | process 1 volt         = &nbsp;
 | process 1 delta from   = [[5 nm]] Δ
 | process 1 fin pitch    = &nbsp;
 | process 1 fin pitch Δ  = &nbsp;
 | process 1 fin width    = &nbsp;
 | process 1 fin width Δ  = &nbsp;
 | process 1 fin height   = &nbsp;
 | process 1 fin height Δ = &nbsp;
 | process 1 gate len     = &nbsp;
 | process 1 gate len Δ   = &nbsp;
 | process 1 cpp          = &nbsp;
 | process 1 cpp Δ        = &nbsp;
 | process 1 mmp          = &nbsp;
 | process 1 mmp Δ        = &nbsp;
 | process 1 sram hp      = &nbsp;
 | process 1 sram hp Δ    = &nbsp;
 | process 1 sram hd      = &nbsp;
 | process 1 sram hd Δ    = &nbsp;
 | process 1 sram lv      = &nbsp;
 | process 1 sram lv Δ    = &nbsp;
 | process 1 dram         = &nbsp;
 | process 1 dram Δ       = &nbsp;
<!-- TSMC -->
 | process 2 fab          = [[TSMC]]
 | process 2 name         = N3, N3E <info>N3 Enhanced</info>
 | process 2 date         = 2H 2022
 | process 2 lith         = EUV
 | process 2 immersion    = &nbsp;
 | process 2 exposure     = SE
 | process 2 wafer type   = Bulk
 | process 2 wafer size   = 300 mm
 | process 2 transistor   = FinFET
 | process 2 volt         = &nbsp;
 | process 2 delta from   = [[5 nm]] Δ
 | process 2 fin pitch    = &nbsp;
 | process 2 fin pitch Δ  = &nbsp;
 | process 2 fin width    = &nbsp;
 | process 2 fin width Δ  = &nbsp;
 | process 2 fin height   = &nbsp;
 | process 2 fin height Δ = &nbsp;
 | process 2 gate len     = &nbsp;
 | process 2 gate len Δ   = &nbsp;
 | process 2 cpp          = &nbsp;
 | process 2 cpp Δ        = &nbsp;
 | process 2 mmp          = &nbsp;
 | process 2 mmp Δ        = &nbsp;
 | process 2 sram hp      = &nbsp;
 | process 2 sram hp Δ    = &nbsp;
 | process 2 sram hd      = &nbsp;
 | process 2 sram hd Δ    = &nbsp;
 | process 2 sram lv      = &nbsp;
 | process 2 sram lv Δ    = &nbsp;
 | process 2 dram         = &nbsp;
 | process 2 dram Δ       = &nbsp;
<!-- Samsung -->
 | process 4 fab          = [[Samsung]]
 | process 4 name         = 3GAE<info>3nm Gate All Around Early</info>, 3GAP<info>3nm Gate All Around Plus</info>
 | process 4 date         = &nbsp;
 | process 4 lith         = EUV
 | process 4 immersion    = &nbsp;
 | process 4 exposure     = SE
 | process 4 wafer type   = Bulk
 | process 4 wafer size   = 300 mm
 | process 4 transistor   = GAA
 | process 4 volt         = &nbsp;
 | process 4 delta from   = [[5 nm]] Δ
 | process 4 fin pitch    = -
 | process 4 fin pitch Δ  = 
 | process 4 fin width    = 
 | process 4 fin width Δ  = 
 | process 4 fin height   = 
 | process 4 fin height Δ = 
 | process 4 gate len     = &nbsp;
 | process 4 gate len Δ   = &nbsp;
 | process 4 cpp          = &nbsp;
 | process 4 cpp Δ        = &nbsp;
 | process 4 mmp          = &nbsp;
 | process 4 mmp Δ        = &nbsp;
 | process 4 sram hp      = &nbsp;
 | process 4 sram hp Δ    = &nbsp;
 | process 4 sram hd      = &nbsp;
 | process 4 sram hd Δ    = &nbsp;
 | process 4 sram lv      = &nbsp;
 | process 4 sram lv Δ    = &nbsp;
 | process 4 dram         = &nbsp;
 | process 4 dram Δ       = &nbsp;
}}
==== P1278 ====
Intel's 5-nanometer (renamed as Intel 20A) process node is expected to ramp around the 2H2024/2025 timeframe. 
=== Samsung ===
On May 24 2017 Samsung announced they will be switching to a transistor they call ''Multi-Bridge-Channel FET'' (''MBCFET''), an extension of a  [[Gate-all-around]] (GAA) FET. This is planned for somewhere after the 5nm node but the exact timeline or specification is currently unknown.

=== TSMC ===
N3 technology will offer up to 70% logic density gain, up to 15% speed improvement at the same power and up to 30% power reduction at the same speed as compared with N5 technology (According to TSMCs website). If this holds true we could see 300+ MT/mm2.

== 3 nm Microprocessors==

{{expand list}}

== 3 nm Microarchitectures==
{{expand list}}

== References ==
* Kinam Kim, President of Semiconductor Business, announced MBCFET for the node after [[5 nm]], May 24, 2017

[[category:lithography]]