From WikiChip
Difference between revisions of "32 nm lithography process"

(Design Rules)
Line 46: Line 46:
 
{| class="wikitable collapsible collapsed"
 
{| class="wikitable collapsible collapsed"
 
|-
 
|-
! colspan="4" | Intel 32nm Design Rules
+
! colspan="5" | Intel 32nm Design Rules
 
|-
 
|-
! Layer !! Pitch !! Thick !! Aspect Ratio
+
! Layer !! Pitch !! Thick !! Aspect Ratio !! Image
 
|-
 
|-
| Isolation || 140 nm || 200 || -
+
| Isolation || 140 nm || 200 || - || rowspan="11" | [[file:intel 32nm design rules.png|750px]]
 
|-
 
|-
 
| Contacted Gate ||  112.5 nm || 35 nm || --
 
| Contacted Gate ||  112.5 nm || 35 nm || --

Revision as of 20:10, 30 November 2016

The 32 nanometer (32 nm) lithography process is a full node semiconductor manufacturing process following the 40 nm process stopgap. Commercial integrated circuit manufacturing using 32 nm process began in 2010. This technology was superseded by the 28 nm process (HN) / 22 nm process (FN) in 2012.

Industry

TSMC cancelled its planned 32nm node process.

Fab
Process Name​
1st Production​
Type​
Wafer​
 ​
Contacted Gate Pitch​
Interconnect Pitch (M1P)​
SRAM bit cell (HD)​
SRAM bit cell (HS)​
SRAM bit cell (LP)​
DRAM bit cell
Common Platform Intel TSMC Samsung Toshiba / NEC Common Platform 2
P1268
2009 2009 2009 2009 2009 2010
PDSOI Bulk
300mm
Value 45 nm Δ Value 45 nm Δ Value 40 nm Δ Value 40 nm Δ Value 40 nm Δ Value 45 nm Δ
130 nm 0.68x 112.5 nm 0.63x 130 nm 0.80x 113.4 nm 0.88x 120 nm 0.71x 126 nm 0.66x
 ? nm  ?x 112.5 nm 0.70x  ? nm  ?x 113.4 nm 0.97x  ? nm  ?x  ?nm  ?x
0.15 µm2 0.41x 0.148 µm2 0.43x 0.15 µm2 0.62x 0.120 µm2  ?x 0.124 µm2 0.64x 0.157 µm2 0.42x
0.199 µm2
0.171 µm2 0.45x
0.039 µm2 0.58x

Design Rules

Find models

Click to browse all 32 nm MPU models

32 nm Microprocessors

This list is incomplete; you can help by expanding it.

32 nm Microarchitectures

This list is incomplete; you can help by expanding it.