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3.5 µm lithography process
Revision as of 17:31, 4 June 2016 by ChipIt (talk | contribs) (Industry)

The 3.5 μm lithography process was the semiconductor process technology used by some semiconductor companies during the mid 1970s. This process had an effective channel length of roughly 3.5 µm between the source and drain. This process was later superseded by 3 µm, 2 µm, and 1.5 µm processes.

Industry

Fab
Process Name​
1st Production​
Contacted Gate Pitch​
Interconnect Pitch​
Metal Layers​
Technology​
Wafer
Intel Intel Motorola
HMOS-I HMOS-E  
1977    
 ? nm  ? nm  ? nm
 ? nm  ? nm  ? nm
1 2  ?
nMOS nMOS nMOS
 ?"  ?"  ?"

3.5 μm microcontrollers

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