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{{lithography processes}}
 
{{lithography processes}}
The '''28 nm lithography process''' is a [[technology node#half node|half-node]] semiconductor manufacturing process used as a stopgap between the [[32 nm lithography process|32 nm]] and [[22 nm lithography process|22 nm]] processes. Commercial [[integrated circuit]] manufacturing using 28 nm process began in 2011. This technology superseded by commercial [[22 nm lithography process|22 nm process]].
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The '''28 nanometer (28 nm) lithography process''' is a [[technology node#half node|half-node]] semiconductor manufacturing process used as a stopgap between the [[32 nm lithography process|32 nm]] and [[22 nm lithography process|22 nm]] processes. Commercial [[integrated circuit]] manufacturing using 28 nm process began in 2011. This technology superseded by commercial [[22 nm lithography process|22 nm process]].
  
 
== Industry ==
 
== Industry ==
 
+
{{nodes comp
=== Samsung ===
+
<!-- TSMC -->
{| class="wikitable"
+
| process 1 fab          = [[TSMC]]
|-
+
| process 1 name        = 28LP, 28HPL, 28HP
| || Measurement || Scaling from [[40 nm]]
+
| process 1 date        = 4Q 2011
|-
+
| process 1 lith        = 193 nm
| Contacted Gate Pitch || 90 nm || 0.70x
+
| process 1 immersion    = Yes
|-
+
| process 1 exposure    = DP
| Interconnect Pitch (M1P) || 96 nm || 0.82x
+
| process 1 wafer type  = Bulk
|-
+
| process 1 wafer size  = 300 mm
| [[SRAM]] bit cell || 0.120 µm<sup>2</sup> || ?x
+
| process 1 transistor  = Planar
|}
+
| process 1 volt        = 1 V, 0.8 V
 
+
| process 1 layers      = 10
=== TSMC ===
+
| process 1 delta from   = [[32 nm]] Δ
{| class="wikitable"
+
| process 1 gate len    = 24 nm
|-
+
| process 1 gate len Δ  = &nbsp;
| || Measurement || Notes
+
| process 1 cpp          = 117 nm
|-
+
| process 1 cpp Δ        = &nbsp;
| Contacted Gate Pitch || 117 nm ||
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| process 1 mmp          = 90 nm
|-
+
| process 1 mmp Δ        = &nbsp;
| Interconnect Pitch (M1P) || ? nm ||
+
| process 1 sram hp      = &nbsp;
|-
+
| process 1 sram hp Δ    = &nbsp;
| [[SRAM]] bit cell || 0.127 µm<sup>2</sup> || High Density
+
| process 1 sram hd      = 0.127 µm²
|-
+
| process 1 sram hd Δ    = &nbsp;
| [[SRAM]] bit cell || 0.155 µm<sup>2</sup> || Low Voltage
+
| process 1 sram lv      = 0.155 µm²
|}
+
| process 1 sram lv Δ    = &nbsp;
 +
| process 1 dram        = &nbsp;
 +
| process 1 dram Δ      = &nbsp;
 +
<!-- IBM -->
 +
| process 2 fab          = [[Common Platform Alliance ]]<info>The '''Common Platform Alliance''' is a joint collaboration between [[IBM]], [[Samsung]], [[GlobalFoundries]], [[Toshiba]], [[NEC]], [[STMicroelectronics]], [[Infineon Technologies]], [[Chartered Semiconductor Manufacturing]], [[Renasas]]</info>
 +
| process 2 name        = 28LP, 28LPP, 28SLP
 +
| process 2 date        = 2014
 +
| process 2 lith        = 193 nm
 +
| process 2 immersion    = Yes
 +
| process 2 exposure    = DP
 +
| process 2 wafer type  = Bulk
 +
| process 2 wafer size  = 300 mm
 +
| process 2 transistor  = Planar
 +
| process 2 volt        = 1 V, 0.85 V
 +
| process 2 layers      = 10
 +
| process 2 delta from  = [[32 nm]] Δ
 +
| process 2 gate len    = 28 nm
 +
| process 2 gate len Δ  = &nbsp;
 +
| process 2 cpp          = 113.4 nm
 +
| process 2 cpp Δ        = &nbsp;
 +
| process 2 mmp          = 90 nm
 +
| process 2 mmp Δ        = &nbsp;
 +
| process 2 sram hp      = 0.152 µm²
 +
| process 2 sram hp Δ    = &nbsp;
 +
| process 2 sram hd      = 0.120 µm²
 +
| process 2 sram hd Δ    = &nbsp;
 +
| process 2 sram lv      = 0.197 µm²
 +
| process 2 sram lv Δ    = &nbsp;
 +
| process 2 dram        = &nbsp;
 +
| process 2 dram Δ      = &nbsp;
 +
<!-- UMC -->
 +
| process 3 fab          = [[UMC]]
 +
| process 3 name        = 28HPC, 28HLP, 28HPC+, 28µLP
 +
| process 3 date        = 2013
 +
| process 3 lith        = 193 nm
 +
| process 3 immersion    = Yes
 +
| process 3 exposure    = DP
 +
| process 3 wafer type  = Bulk
 +
| process 3 wafer size  = 300 mm
 +
| process 3 transistor  = Planar
 +
| process 3 volt        = 0.9 V, 1.05 V, 0.7 V
 +
| process 3 layers      = 10
 +
| process 3 delta from  = [[40 nm]] Δ
 +
| process 3 gate len    = 33 nm
 +
| process 3 gate len Δ  = &nbsp;
 +
| process 3 cpp          = 120 nm
 +
| process 3 cpp Δ        = &nbsp;
 +
| process 3 mmp          = 90 nm
 +
| process 3 mmp Δ        = &nbsp;
 +
| process 3 sram hp      = &nbsp;
 +
| process 3 sram hp Δ    = &nbsp;
 +
| process 3 sram hd      = 0.124 µm²
 +
| process 3 sram hd Δ    = &nbsp;
 +
| process 3 sram lv      = &nbsp;
 +
| process 3 sram lv Δ    = &nbsp;
 +
| process 3 dram        = &nbsp;
 +
| process 3 dram Δ      = &nbsp;
 +
<!-- SMIC -->
 +
| process 4 fab          = [[SMIC]]
 +
| process 4 name        = 28PS, 28HK, 28HKC+
 +
| process 4 date        = 4Q 2013
 +
| process 4 lith        = &nbsp;
 +
| process 4 immersion    = &nbsp;
 +
| process 4 exposure    = &nbsp;
 +
| process 4 wafer type  = &nbsp;
 +
| process 4 wafer size  = &nbsp;
 +
| process 4 transistor  = &nbsp;
 +
| process 4 volt        = 1.8 V, 2.5 V
 +
| process 4 layers      = &nbsp;
 +
| process 4 delta from  = &nbsp;
 +
| process 4 gate len    = &nbsp;
 +
| process 4 gate len Δ  = &nbsp;
 +
| process 4 cpp          = &nbsp;
 +
| process 4 cpp Δ        = &nbsp;
 +
| process 4 mmp          = &nbsp;
 +
| process 4 mmp Δ        = &nbsp;
 +
| process 4 sram hp      = &nbsp;
 +
| process 4 sram hp Δ    = &nbsp;
 +
| process 4 sram hd      = &nbsp;
 +
| process 4 sram hd Δ    = &nbsp;
 +
| process 4 sram lv      = &nbsp;
 +
| process 4 sram lv Δ    = &nbsp;
 +
| process 4 dram        = &nbsp;
 +
| process 4 dram Δ      = &nbsp;
 +
}}
  
 
== 28 nm Microprocessors ==
 
== 28 nm Microprocessors ==
 
* AMD
 
* AMD
 
** {{amd|A8}}
 
** {{amd|A8}}
** {{amd|A10}}
+
** {{amd|A10}}  
 +
**A9
 +
* HiSilicon
 +
** {{hisil|Kirin}}
 +
* Intel (Fab'ed by [[TSMC]])
 +
** {{intel|Atom x3}}
 +
* MediaTek
 +
** {{mediatek|Helio}}
 +
* Phytium
 +
** {{phytium|FT-1500A}}
 +
* PEZY
 +
** {{pezy|PEZY-SC}}
 +
** {{pezy|PEZY-SCnp}}
 +
* Renesas
 +
** {{renesas|R-Car}}
 +
* Xiaomi
 +
** {{xiaomi|Surge}}
 +
 
 
{{expand list}}
 
{{expand list}}
== 28 nm System on Chips ==
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* Intel
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== 28 nm Microarchitectures ==
** {{intel|Atom x3}}
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* AMD
 +
** {{amd|Steamroller|l=arch}}
 +
** {{amd|Excavator|l=arch}}
 +
* ARM Holdings
 +
** {{armh|Cortex-A53|l=arch}}
 +
* Nervana
 +
** {{nervana|Lake Crest|l=arch}}
 +
* Movidius
 +
** {{movidius|SHAVE v3.0|l=arch}}
 +
* Phytium
 +
** {{phytium|Xiaomi|l=arch}}
 +
** {{phytium|Mars I|l=arch}}
 +
* VIA Technologies
 +
** {{via|Isaiah II|l=arch}}
 +
* Zhaoxin
 +
** {{zhaoxin|ZhangJiang|l=arch}}
 +
** {{zhaoxin|WuDaoKou|l=arch}}
  
 
{{expand list}}
 
{{expand list}}
 +
 +
== References ==
 +
* [[:File:samsung foundry solution 28-32nm.pdf|Samsung foundry solution for 32 & 28 nm]]
 +
* Wu, Shien-Yang, et al. "A highly manufacturable 28nm cmos low power platform technology with fully functional 64mb sram using dual/tripe gate oxide process." VLSI Technology, 2009 Symposium on. IEEE, 2009.
 +
* Shang, Huiling, et al. "High performance bulk planar 20nm CMOS technology for low power mobile applications." VLSI Technology (VLSIT), 2012 Symposium on. IEEE, 2012.
 +
* Arnaud, F., et al. "Competitive and cost effective high-k based 28nm CMOS technology for low power applications." Electron Devices Meeting (IEDM), 2009 IEEE International. IEEE, 2009.
 +
* Yuan, J., et al. "Performance elements for 28nm gate length bulk devices with gate first high-k metal gate." Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on. IEEE, 2010.
 +
* Liang, C. W., et al. "A 28nm poly/SiON CMOS technology for low-power SoC applications." VLSI Technology (VLSIT), 2011 Symposium on. IEEE, 2011.
 +
* James, Dick. "High-k/metal gates in the 2010s." Advanced Semiconductor Manufacturing Conference (ASMC), 2014 25th Annual SEMI. IEEE, 2014.
 +
 +
[[category:lithography]]

Latest revision as of 17:01, 26 March 2019

The 28 nanometer (28 nm) lithography process is a half-node semiconductor manufacturing process used as a stopgap between the 32 nm and 22 nm processes. Commercial integrated circuit manufacturing using 28 nm process began in 2011. This technology superseded by commercial 22 nm process.

Industry[edit]

 
Process Name
1st Production
Lithography Lithography
Immersion
Exposure
Wafer Type
Size
Transistor Type
Voltage
Metal Layers
 
Gate Length (Lg)
Contacted Gate Pitch (CPP)
Minimum Metal Pitch (MMP)
SRAM bitcell High-Perf (HP)
High-Density (HD)
Low-Voltage (LV)
DRAM bitcell eDRAM
TSMC Common Platform Alliance UMC SMIC
28LP, 28HPL, 28HP 28LP, 28LPP, 28SLP 28HPC, 28HLP, 28HPC+, 28µLP 28PS, 28HK, 28HKC+
4Q 2011 2014 2013 4Q 2013
193 nm 193 nm 193 nm  
Yes Yes Yes  
DP DP DP  
Bulk Bulk Bulk  
300 mm 300 mm 300 mm  
Planar Planar Planar  
1 V, 0.8 V 1 V, 0.85 V 0.9 V, 1.05 V, 0.7 V 1.8 V, 2.5 V
10 10 10  
Value 32 nm Δ Value 32 nm Δ Value 40 nm Δ Value  
24 nm   28 nm   33 nm      
117 nm   113.4 nm   120 nm      
90 nm   90 nm   90 nm      
    0.152 µm²          
0.127 µm²   0.120 µm²   0.124 µm²      
0.155 µm²   0.197 µm²          
               

28 nm Microprocessors[edit]

This list is incomplete; you can help by expanding it.

28 nm Microarchitectures[edit]

This list is incomplete; you can help by expanding it.

References[edit]

  • Samsung foundry solution for 32 & 28 nm
  • Wu, Shien-Yang, et al. "A highly manufacturable 28nm cmos low power platform technology with fully functional 64mb sram using dual/tripe gate oxide process." VLSI Technology, 2009 Symposium on. IEEE, 2009.
  • Shang, Huiling, et al. "High performance bulk planar 20nm CMOS technology for low power mobile applications." VLSI Technology (VLSIT), 2012 Symposium on. IEEE, 2012.
  • Arnaud, F., et al. "Competitive and cost effective high-k based 28nm CMOS technology for low power applications." Electron Devices Meeting (IEDM), 2009 IEEE International. IEEE, 2009.
  • Yuan, J., et al. "Performance elements for 28nm gate length bulk devices with gate first high-k metal gate." Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on. IEEE, 2010.
  • Liang, C. W., et al. "A 28nm poly/SiON CMOS technology for low-power SoC applications." VLSI Technology (VLSIT), 2011 Symposium on. IEEE, 2011.
  • James, Dick. "High-k/metal gates in the 2010s." Advanced Semiconductor Manufacturing Conference (ASMC), 2014 25th Annual SEMI. IEEE, 2014.