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Difference between revisions of "28 nm lithography process"

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== Industry ==
 
== Industry ==
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{{scrolling table/top|style=text-align: right; | first=Fab
+
{{nodes comp
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  |Process Name
+
<!-- TSMC -->
−
  |Transistor
+
| process 1 fab          = [[TSMC]]
−
  |Wafer
+
| process 1 name        = &nbsp;
−
  |Metal Layers
+
| process 1 date        = &nbsp;
−
  |&nbsp;
+
| process 1 lith        = &nbsp;
−
  |Contacted Gate Pitch
+
| process 1 immersion    = &nbsp;
−
  |Interconnect Pitch (M1P)
+
| process 1 exposure    = &nbsp;
−
  |SRAM bit cell (HD)
+
| process 1 wafer type  = Bulk
−
  |SRAM bit cell (LP)
+
| process 1 wafer size  = 300 mm
−
  |SRAM bit cell (HC)
+
| process 1 transistor  = Planar
 +
| process 1 volt        = &nbsp;
 +
| process 1 layers      = 10
 +
| process 1 delta from  = [[32 nm]] Δ
 +
| process 1 gate len    = &nbsp;
 +
| process 1 gate len Δ  = &nbsp;
 +
| process 1 cpp          = &nbsp;
 +
| process 1 cpp Δ        = &nbsp;
 +
| process 1 mmp          = &nbsp;
 +
| process 1 mmp Δ        = &nbsp;
 +
| process 1 sram hp      = &nbsp;
 +
| process 1 sram hp Δ    = &nbsp;
 +
| process 1 sram hd      = &nbsp;
 +
| process 1 sram hd Δ    = &nbsp;
 +
| process 1 sram lv      = &nbsp;
 +
| process 1 sram lv Δ    = &nbsp;
 +
| process 1 dram        = &nbsp;
 +
| process 1 dram Δ      = &nbsp;
 +
<!-- IBM -->
 +
| process 2 fab          = [[Common Platform Alliance ]]<info>The '''Common Platform Alliance '' is a joint collaboration between [[IBM]], [[Samsung]], [[GlobalFoundries]], [[Toshiba]], [[NEC]], [[STMicroelectronics]], [[Infineon Technologies]], [[Chartered Semiconductor Manufacturing]]</info>
 +
| process 2 name        = 28LP/28LPP/28SLP
 +
| process 2 date        = 2
 +
| process 2 lith        = &nbsp;
 +
| process 2 immersion    = &nbsp;
 +
| process 2 exposure    = &nbsp;
 +
| process 2 wafer type  = Bulk
 +
| process 2 wafer size  = 300 mm
 +
| process 2 transistor  = Planar
 +
| process 2 volt        = 1 V
 +
| process 2 layers      = &nbsp;
 +
| process 2 delta from  = [[32 nm]] Δ
 +
| process 2 gate len    = &nbsp;
 +
| process 2 gate len Δ  = &nbsp;
 +
| process 2 cpp          = 113.4 nm
 +
  | process 2 cpp Δ        = &nbsp;
 +
  | process 2 mmp          = 90 nm
 +
  | process 2 mmp Δ        = &nbsp;
 +
  | process 2 sram hp      = 0.152 µm²
 +
  | process 2 sram hp Δ    = &nbsp;
 +
  | process 2 sram hd      = 0.120 µm²
 +
  | process 2 sram hd Δ    = &nbsp;
 +
  | process 2 sram lv      = 0.197 µm²
 +
  | process 2 sram lv Δ    = &nbsp;
 +
  | process 2 dram        = &nbsp;
 +
| process 2 dram Δ      = &nbsp;
 
}}
 
}}
−
{{scrolling table/mid}}
 
−
|-
 
−
! colspan="2" | [[Samsung]] !! colspan="2" | [[TSMC]] !! colspan="2" | [[GlobalFoundries]] !! colspan="2" | [[STMicroelectronics]] !! colspan="2" | [[UMC]]
 
−
|- style="text-align: center;"
 
−
| colspan="2" | 28LP/28LPP || colspan="2" | &nbsp; || colspan="2" | 28SLP || colspan="2" | &nbsp; || colspan="2" | &nbsp;
 
−
|- style="text-align: center;"
 
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| colspan="10" | Planar
 
−
|- style="text-align: center;"
 
−
| colspan="10" | 300 mm
 
−
|- style="text-align: center;"
 
−
| colspan="2" | &nbsp; || colspan="2" | 10 || colspan="2" | &nbsp; || colspan="2" | &nbsp; || colspan="2" | &nbsp;
 
−
|-
 
−
! Value !! [[40 nm]] Δ !! Value !! [[40 nm]] Δ !! Value !! [[40 nm]] Δ !! Value !! [[40 nm]] Δ !! Value !! [[40 nm]] Δ
 
−
|-
 
−
| 113.4 nm || 0.88x || 117 nm || 0.72x || 113.4 nm || ?x || ?nm || ?x || ?nm || ?x
 
−
|-
 
−
| 90 nm || 0.76x || 95 nm || 0.81x || 90 nm || ?x || ?nm || ?x || ?nm || ?x
 
−
|-
 
−
| 0.120 µm² || ?x || 0.127 µm² || 0.52x || 0.120 µm² || ?x || 0.120 µm² || ?x || 0.124 µm² || ?x
 
−
|-
 
−
|  || || 0.155 µm² || || || || 0.197 µm² || ?x || ? µm² || ?x
 
−
|-
 
−
|  || || || || || || 0.152 µm² || ?x || ||
 
−
{{scrolling table/end}}
 
  
 
== 28 nm Microprocessors ==
 
== 28 nm Microprocessors ==

Revision as of 02:10, 6 April 2017

basic wafer drawing.svg Semiconductor lithography processes technology
v · d · e

The 28 nanometer (28 nm) lithography process is a half-node semiconductor manufacturing process used as a stopgap between the 32 nm and 22 nm processes. Commercial integrated circuit manufacturing using 28 nm process began in 2011. This technology superseded by commercial 22 nm process.

Industry

 
Process Name
1st Production
Lithography Lithography
Immersion
Exposure
Wafer Type
Size
Transistor Type
Voltage
Metal Layers
 
Gate Length (Lg)
Contacted Gate Pitch (CPP)
Minimum Metal Pitch (MMP)
SRAM bitcell High-Perf (HP)
High-Density (HD)
Low-Voltage (LV)
DRAM bitcell eDRAM
TSMC Common Platform Alliance
The 'Common Platform Alliance is a joint collaboration between IBM, Samsung, GlobalFoundries, Toshiba, NEC, STMicroelectronics, Infineon Technologies, Chartered Semiconductor Manufacturing
  28LP/28LPP/28SLP
  2
   
   
   
Bulk Bulk
300 mm 300 mm
Planar Planar
  1 V
10  
Value 32 nm Δ Value 32 nm Δ
       
    113.4 nm  
    90 nm  
    0.152 µm²  
    0.120 µm²  
    0.197 µm²  
       

28 nm Microprocessors

This list is incomplete; you can help by expanding it.

28 nm Microarchitectures

This list is incomplete; you can help by expanding it.

References

  • Wu, Shien-Yang, et al. "A highly manufacturable 28nm cmos low power platform technology with fully functional 64mb sram using dual/tripe gate oxide process." VLSI Technology, 2009 Symposium on. IEEE, 2009.
  • Shang, Huiling, et al. "High performance bulk planar 20nm CMOS technology for low power mobile applications." VLSI Technology (VLSIT), 2012 Symposium on. IEEE, 2012.
  • James, Dick. "High-k/metal gates in the 2010s." Advanced Semiconductor Manufacturing Conference (ASMC), 2014 25th Annual SEMI. IEEE, 2014.
  • Samsung foundry solution for 32 & 28 nm
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