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Difference between revisions of "28 nm lithography process"
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== Industry == | == Industry == | ||
{{scrolling table/top|style=text-align: right; | first=Fab | {{scrolling table/top|style=text-align: right; | first=Fab | ||
+ | |Process Name | ||
|Transistor | |Transistor | ||
|Wafer | |Wafer | ||
+ | |Metal Layers | ||
| | | | ||
|Contacted Gate Pitch | |Contacted Gate Pitch | ||
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|- | |- | ||
! colspan="2" | [[Samsung]] !! colspan="2" | [[TSMC]] !! colspan="2" | [[GlobalFoundries]] !! colspan="2" | [[STMicroelectronics]] !! colspan="2" | [[UMC]] | ! colspan="2" | [[Samsung]] !! colspan="2" | [[TSMC]] !! colspan="2" | [[GlobalFoundries]] !! colspan="2" | [[STMicroelectronics]] !! colspan="2" | [[UMC]] | ||
+ | |- style="text-align: center;" | ||
+ | | colspan="2" | 28LP/28LPP || colspan="2" | || colspan="2" | 28SLP || colspan="2" | || colspan="2" | | ||
|- style="text-align: center;" | |- style="text-align: center;" | ||
| colspan="10" | Planar | | colspan="10" | Planar | ||
|- style="text-align: center;" | |- style="text-align: center;" | ||
| colspan="10" | 300 mm | | colspan="10" | 300 mm | ||
+ | |- style="text-align: center;" | ||
+ | | colspan="2" | || colspan="2" | 10 || colspan="2" | || colspan="2" | || colspan="2" | | ||
|- | |- | ||
! Value !! [[40 nm]] Δ !! Value !! [[40 nm]] Δ !! Value !! [[40 nm]] Δ !! Value !! [[40 nm]] Δ !! Value !! [[40 nm]] Δ | ! Value !! [[40 nm]] Δ !! Value !! [[40 nm]] Δ !! Value !! [[40 nm]] Δ !! Value !! [[40 nm]] Δ !! Value !! [[40 nm]] Δ | ||
|- | |- | ||
− | | | + | | 113.4 nm || 0.88x || 117 nm || 0.72x || 113.4 nm || ?x || ?nm || ?x || ?nm || ?x |
|- | |- | ||
− | | | + | | 90 nm || 0.76x || 95 nm || 0.81x || 90 nm || ?x || ?nm || ?x || ?nm || ?x |
|- | |- | ||
| 0.120 µm² || ?x || 0.127 µm² || 0.52x || 0.120 µm² || ?x || 0.120 µm² || ?x || 0.124 µm² || ?x | | 0.120 µm² || ?x || 0.127 µm² || 0.52x || 0.120 µm² || ?x || 0.120 µm² || ?x || 0.124 µm² || ?x | ||
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{{expand list}} | {{expand list}} | ||
+ | |||
+ | == References == | ||
+ | * Wu, Shien-Yang, et al. "A highly manufacturable 28nm cmos low power platform technology with fully functional 64mb sram using dual/tripe gate oxide process." VLSI Technology, 2009 Symposium on. IEEE, 2009. | ||
+ | * Shang, Huiling, et al. "High performance bulk planar 20nm CMOS technology for low power mobile applications." VLSI Technology (VLSIT), 2012 Symposium on. IEEE, 2012. | ||
+ | * James, Dick. "High-k/metal gates in the 2010s." Advanced Semiconductor Manufacturing Conference (ASMC), 2014 25th Annual SEMI. IEEE, 2014. | ||
+ | * [[:File:samsung foundry solution 28-32nm.pdf|Samsung foundry solution for 32 & 28 nm]] |
Revision as of 20:01, 28 March 2017
The 28 nanometer (28 nm) lithography process is a half-node semiconductor manufacturing process used as a stopgap between the 32 nm and 22 nm processes. Commercial integrated circuit manufacturing using 28 nm process began in 2011. This technology superseded by commercial 22 nm process.
Industry
Fab |
---|
Process Name |
Transistor |
Wafer |
Metal Layers |
|
Contacted Gate Pitch |
Interconnect Pitch (M1P) |
SRAM bit cell (HD) |
SRAM bit cell (LP) |
SRAM bit cell (HC) |
Samsung | TSMC | GlobalFoundries | STMicroelectronics | UMC | |||||
---|---|---|---|---|---|---|---|---|---|
28LP/28LPP | 28SLP | ||||||||
Planar | |||||||||
300 mm | |||||||||
10 | |||||||||
Value | 40 nm Δ | Value | 40 nm Δ | Value | 40 nm Δ | Value | 40 nm Δ | Value | 40 nm Δ |
113.4 nm | 0.88x | 117 nm | 0.72x | 113.4 nm | ?x | ?nm | ?x | ?nm | ?x |
90 nm | 0.76x | 95 nm | 0.81x | 90 nm | ?x | ?nm | ?x | ?nm | ?x |
0.120 µm² | ?x | 0.127 µm² | 0.52x | 0.120 µm² | ?x | 0.120 µm² | ?x | 0.124 µm² | ?x |
0.155 µm² | 0.197 µm² | ?x | ? µm² | ?x | |||||
0.152 µm² | ?x |
28 nm Microprocessors
- AMD
- Intel (Fab'ed by TSMC)
- MediaTek
- Phytium
- PEZY
- Xiaomi
This list is incomplete; you can help by expanding it.
28 nm Microarchitectures
- AMD
- ARM Holdings
- Phytium
This list is incomplete; you can help by expanding it.
References
- Wu, Shien-Yang, et al. "A highly manufacturable 28nm cmos low power platform technology with fully functional 64mb sram using dual/tripe gate oxide process." VLSI Technology, 2009 Symposium on. IEEE, 2009.
- Shang, Huiling, et al. "High performance bulk planar 20nm CMOS technology for low power mobile applications." VLSI Technology (VLSIT), 2012 Symposium on. IEEE, 2012.
- James, Dick. "High-k/metal gates in the 2010s." Advanced Semiconductor Manufacturing Conference (ASMC), 2014 25th Annual SEMI. IEEE, 2014.
- Samsung foundry solution for 32 & 28 nm