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Editing 280 nm lithography process

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== Industry ==
 
== Industry ==
Around 1996 Intel introduced a stopgap shrink between [[0.35 µm]] and [[0.25 µm]]. Unlike [[0.35 µm]] which used BiCMOS process for their {{intel|Pentium}} and {{intel|Pentium Pro}} processors, the 0.28 µm process was a standard CMOS process. Featuring a smaller transistor gate pitch, the process shared similar metal layer sizes to the [[0.35 µm]] (this is why some Intel documents refer to it as "0.35µm"). The process was used in Intel's {{intel|P55C}} ({{x86|MMX}}) and {{intel|P6|l=arch}} {{intel|Klamath|l=core}} core-based and models. The semi-shrink which resulted in smaller transistors and improved switching speed was done to compensate for the return to CMOS (i.e., lack of fast bipolar transistors).  
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Around 1996 Intel introduced a stopgap shrink between [[0.35 µm]] and [[0.25 µm]]. Unlike [[0.35 µm]] which used BiCMOS process for their {{intel|Pentium}} and {{intel|Pentium Pro}} processors, the 0.28 µm process was a standard CMOS process. Featuring a smaller transistor gate pitch, the process shared similar metal layer sizes to the [[0.35 µm]] (this is why some Intel documents refer to it as "0.35µm"). The process was used in Intel's {{intel|P55C}} and {{intel|P6|l=arch}} {{intel|Klamath|l=core}} core-based and models. The semi-shrink which resulted in smaller transistors and improved switching speed was done to compensate for the return to CMOS (i.e., lack of fast bipolar transistors).  
 
{{scrolling table/top|style=text-align: right; | first=Fab
 
{{scrolling table/top|style=text-align: right; | first=Fab
 
  |Process Name
 
  |Process Name

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