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Difference between revisions of "250 nm lithography process"

(Industry)
(Industry)
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The 0.25 µm-based process entered production at [[Intel]] in 1997. Intel original 0.25 micron process was named ''P856'' or ''Process 856''. A second process, named ''P856.5'', was a 5% linear shrink of the original design rules. The shrink, which enabled a high equipment re-use resulted in a smaller, 9.26 µm<sup>2</sup>, 6T SRAM. The process used 200 mm [[wafer]]s, [[Wikipedia:SiO2|SiO<sub>2</sub>]] dielectric and [[wikipedia:polysilicon|polysilicon]] electode. It used [[wikipedia:Aluminium|Al]] inter-connects and an [[wikipedia:Silicon|Si]] channels.
 
The 0.25 µm-based process entered production at [[Intel]] in 1997. Intel original 0.25 micron process was named ''P856'' or ''Process 856''. A second process, named ''P856.5'', was a 5% linear shrink of the original design rules. The shrink, which enabled a high equipment re-use resulted in a smaller, 9.26 µm<sup>2</sup>, 6T SRAM. The process used 200 mm [[wafer]]s, [[Wikipedia:SiO2|SiO<sub>2</sub>]] dielectric and [[wikipedia:polysilicon|polysilicon]] electode. It used [[wikipedia:Aluminium|Al]] inter-connects and an [[wikipedia:Silicon|Si]] channels.
 
{{scrolling table/top|style=text-align: right; | first=Fab
 
{{scrolling table/top|style=text-align: right; | first=Fab
 +
|Process Name
 
  |Type
 
  |Type
 
  |Contacted Gate Pitch
 
  |Contacted Gate Pitch
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{{scrolling table/mid}}
 
{{scrolling table/mid}}
 
|-
 
|-
! colspan="2" | [[Intel]]
+
! colspan="2" | [[Intel]] || colspan="2" | [[IBM]] || colspan="2" | [[AMD]] || colspan="2" | [[TI]] || colspan="2" | [[DEC]] || colspan="2" | [[IDT]] || colspan="2" | [[Fujitsu]]
 +
|- style="text-align: center;"
 +
| colspan="2" | P856 || colspan="2" | CMOS-6X || colspan="2" | CS-44 || colspan="2" | C07 || colspan="2" | CMOS-7 || colspan="2" | CMOS-10+ || colspan="2" | CS-70
 
|-
 
|-
! Value !! [[350 nm]] Δ
+
! Value !! [[350 nm]] Δ !! Value !! [[350 nm]] Δ !! Value !! [[350 nm]] Δ !! Value !! [[350 nm]] Δ !! Value !! [[350 nm]] Δ !! Value !! [[350 nm]] Δ !! Value !! [[350 nm]] Δ
 
|-
 
|-
| 500 nm || 0.91x
+
| 500 nm || 0.91x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x
 
|-
 
|-
| 608 nm || 0.69x
+
| 640 nm || 0.72x || 700 nm || ?x || 880 nm || ?x || 850 nm || ?x || 840 nm || ?x || 940 nm || ?x || 900 nm || ?x
 
|-
 
|-
| 10.26 µm<sup>2</sup> || 0.57x
+
| 10.26 µm<sup>2</sup> || 0.57x || 8.6 µm<sup>2</sup> || ?x || ? µm<sup>2</sup> || ?x || 10.5 µm<sup>2</sup> || ?x || 11.5 µm<sup>2</sup> || ?x || 11.2 µm<sup>2</sup> || ?x || ? µm<sup>2</sup> || ?x
 
{{scrolling table/end}}
 
{{scrolling table/end}}
 
=== Design Rules ===
 
=== Design Rules ===
 
 
{| class="wikitable collapsible collapsed"
 
{| class="wikitable collapsible collapsed"
 
|-
 
|-

Revision as of 17:47, 24 April 2016

The 250 nm lithography process is a full node semiconductor manufacturing process following the 350 nm process node. Commercial integrated circuit manufacturing using 250 nm process began in 1997 and was eventually replaced by 180 nm by 1999.

Industry

The 0.25 µm-based process entered production at Intel in 1997. Intel original 0.25 micron process was named P856 or Process 856. A second process, named P856.5, was a 5% linear shrink of the original design rules. The shrink, which enabled a high equipment re-use resulted in a smaller, 9.26 µm2, 6T SRAM. The process used 200 mm wafers, SiO2 dielectric and polysilicon electode. It used Al inter-connects and an Si channels.

Fab
Process Name​
Type​
Contacted Gate Pitch​
Interconnect Pitch (M1P)​
SRAM bit cell
Intel IBM AMD TI DEC IDT Fujitsu
P856 CMOS-6X CS-44 C07 CMOS-7 CMOS-10+ CS-70
Value 350 nm Δ Value 350 nm Δ Value 350 nm Δ Value 350 nm Δ Value 350 nm Δ Value 350 nm Δ Value 350 nm Δ
500 nm 0.91x  ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x
640 nm 0.72x 700 nm  ?x 880 nm  ?x 850 nm  ?x 840 nm  ?x 940 nm  ?x 900 nm  ?x
10.26 µm2 0.57x 8.6 µm2  ?x  ? µm2  ?x 10.5 µm2  ?x 11.5 µm2  ?x 11.2 µm2  ?x  ? µm2  ?x

Design Rules

250 nm Microprocessors

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250 nm Microarchitectures

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