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Difference between revisions of "250 nm lithography process"

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(Industry)
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| 10.26 µm<sup>2</sup> || 0.57x
 
| 10.26 µm<sup>2</sup> || 0.57x

Revision as of 10:03, 24 April 2016

The 250 nm lithography process is a full node semiconductor manufacturing process following the 350 nm process node. Commercial integrated circuit manufacturing using 250 nm process began in 1997 and was eventually replaced by 180 nm by 1999.

Industry

The 0.25 µm-based process entered production at Intel in 1997. Intel original 0.25 micron process was named P856 or Process 856. A second process, named P856.5, was a 5% linear shrink of the original design rules. The shrink, which enabled a high equipment re-use resulted in a smaller, 9.26 µm2, 6T SRAM. The process used 200 mm wafers, SiO2 dielectric and polysilicon electode. It used Al inter-connects and an Si channels.

Fab
Type​
Contacted Gate Pitch​
Interconnect Pitch (M1P)​
SRAM bit cell
Intel
Value 350 nm Δ
 ? nm  ?x
608 nm 0.69x
10.26 µm2 0.57x

Design Rules

250 nm Microprocessors

This list is incomplete; you can help by expanding it.

250 nm Microarchitectures

This list is incomplete; you can help by expanding it.