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Difference between revisions of "22 nm lithography process"

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Revision as of 00:29, 24 April 2016

The 22 nm lithography process is a full node semiconductor manufacturing process following the 28 nm process stopgap. Commercial integrated circuit manufacturing using 22 nm process began in 2008 for memory and 2012 for MPUs. This technology was replaced by with 20 nm process (HN) in 2014 and 16 nm process (FN) in late 2015.

Industry

Intel

22 nm was Intel's first generation of Tri-gate FinFET transistors.

Measurement Scaling from 32 nm
Fin Pitch 60 nm
Contacted Gate Pitch 90 nm 0.80x
Interconnect Pitch (M1P) 80 nm 0.71x
SRAM bit cell 0.1080 µm2 High Performance
SRAM bit cell 0.092 µm2 High Density
SoC Interconnect Design Rules
Layer Pitch Process Dielectric Materials CPU SoC
Fin 60 nm - - Fin Fin
Contact 90 nm SAC - Contact Contact
M1 90 nm SAV ULK CDO M1 M1
MT - 1x 80 nm SAV ULK CDO M2/M3 2-6 layers
MT - 1.4x 112 nm SAV ULK CDO M4 Semi-global
MT - 2x 160 nm SAV ULK CDO M5 Semi-global
MT - 3x 240 nm SAV ULK CDO M6 Global Routing
MT - 4x 320 nm
360 nm
Via First LK CDO M7/M8 Global Routing
MT - TOP 14 µm Plate Up Polymer M9 Top Metal

IBM

Measurement
Contacted Gate Pitch 100 nm
Interconnect Pitch (M1P) 80 nm
SRAM bit cell  ? µm2

22 nm Microprocessors

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22 nm System on Chips

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22 nm Microarchitectures

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