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Difference between revisions of "20 nm lithography process"

(Industry)
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== Industry ==
 
== Industry ==
 
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|Wafer
 
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  |Contacted Gate Pitch
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! colspan="2" | [[Samsung]] !! colspan="2" | [[TSMC]]
 
! colspan="2" | [[Samsung]] !! colspan="2" | [[TSMC]]
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| colspan="4" | 300mm
 
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! Value !! [[28 nm]] Δ !! Value !! [[28 nm]] Δ
 
! Value !! [[28 nm]] Δ !! Value !! [[28 nm]] Δ

Revision as of 21:45, 26 April 2016

The 20 nm lithography process is a half-node semiconductor manufacturing process used as a stopgap between the 22 nm and 16 nm processes. The term "20 nm" is simply a commercial name for a generation of a certain size and its technology, as opposed to gate length or half pitch. Commercial integrated circuit manufacturing using 20 nm process began in 2014. This technology superseded by commercial 16 nm process.

Industry

Fab
Wafer​
 ​
Contacted Gate Pitch​
Interconnect Pitch (M1P)​
SRAM bit cell
Samsung TSMC
300mm
Value 28 nm Δ Value 28 nm Δ
64 nm 0.71x 87 nm 0.71x
64 nm 0.67x 67 nm 0.70x
 ? µm2  ?x 0.07 µm2 0.55x

20 nm Microprocessors

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20 nm System on Chips

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20 nm Microarchitectures

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