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Difference between revisions of "20 nm lithography process"

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== Industry ==
 
== Industry ==
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{{scrolling table/top|style=text-align: right; | first=Fab
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=== Samsung ===
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{| class="wikitable"
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|Contacted Gate Pitch
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|Interconnect Pitch (M1P)
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|SRAM bit cell
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}}
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{{scrolling table/mid}}
 
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|-
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| || Measurement || Scaling from [[28 nm]]
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! colspan="2" | [[Samsung]]
 
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| Contacted Gate Pitch || 64 nm || 0.71x
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! Value !! [[28 nm]] Δ
 
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|-
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| Interconnect Pitch (M1P) || 64 nm || 0.67x
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| 64 nm || 0.71x
 
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| [[SRAM]] bit cell || ? µm<sup>2</sup> || ?x
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| 64 nm || 0.67x
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|-
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| ? µm<sup>2</sup> || ?x
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{{scrolling table/end}}
  
 
== 20 nm Microprocessors==
 
== 20 nm Microprocessors==

Revision as of 05:25, 24 April 2016

basic wafer drawing.svg Semiconductor lithography processes technology
v · d · e

The 20 nm lithography process is a half-node semiconductor manufacturing process used as a stopgap between the 22 nm and 16 nm processes. Commercial integrated circuit manufacturing using 20 nm process began in 2014. This technology superseded by commercial 16 nm process.

Industry

Fab
 ​
Contacted Gate Pitch​
Interconnect Pitch (M1P)​
SRAM bit cell
Samsung
Value 28 nm Δ
64 nm 0.71x
64 nm 0.67x
 ? µm2  ?x

20 nm Microprocessors

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20 nm System on Chips

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20 nm Microarchitectures

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