From WikiChip
16 µm lithography process
Revision as of 18:33, 13 April 2016 by At32Hz (talk | contribs)

The 16 µm lithography process was the semiconductor process technology used by the major semiconductor companies during the years of 1965 and 1968. The typical wafer size for this process at companies such as Fairchild was 1.25 inch (32 mm). The standard transistor packages those years were the TO-5 and TO-18 (Transistor Outline) metal-can packages.


Text document with shapes.svg This article is still a stub and needs your attention. You can help improve this article by editing this page and adding the missing information.