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Difference between revisions of "14 nm lithography process"

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Revision as of 15:28, 20 July 2017

The 14 nanometer (14 nm) lithography process is a semiconductor manufacturing process node serving as shrink from the 22 nm process. The term "14 nm" is simply a commercial name for a generation of a certain size and its technology, as opposed to gate length or half pitch. The 14 nm node was introduced in 2014/2015 and is currently getting replaced by the 10 nm process.

Industry

 
Process Name
1st Production
Lithography Lithography
Immersion
Exposure
Wafer Type
Size
Transistor Type
Voltage
 
Fin Pitch
Width
Height
Gate Length (Lg)
Contacted Gate Pitch (CPP)
Minimum Metal Pitch (MMP)
SRAM bitcell High-Perf (HP)
High-Density (HD)
Low-Voltage (LV)
DRAM bitcell eDRAM
Intel Samsung Alliance
Samsung Alliance consists of a process development collaboration between Samsung and GlobalFoundries. GlobalFoundries licenses Samsung's 14nm process at Fab8, New York.
IBM UMC Common Platform Alliance
The Common Platform Alliance is a joint collaboration between IBM, STMicroelectronics
P1272 (CPU) / P1273 (SoC) 14LPE
1st generation; 14 nm Low Power Early
, 14LPP
2nd generation; 14 nm Low Power Performance
, 14LPC
3rd generation; 14 nm Low Power Cost [reduced]
, 14LPU
4th generation; 14 nm Low Power Ultimate
14HP
14nm High Performance
  14FDSOI
2014 2015      
193 nm 193 nm 193 nm 193 nm 193 nm
Yes       Yes
        DP
Bulk Bulk SOI   SOI
300 mm 300 mm 300 mm 300 mm 300 mm
FinFET FinFET FinFET FinFET Planar
0.70 V 0.80 V 0.8 V   0.80 V
Value 22 nm Δ Value 20 nm Δ Value 22 nm Δ Value 28 nm Δ Value 28 nm Δ
42 nm 0.70x 48 nm N/A 42 nm N/A     N/A
8 nm 1.00x 8 nm 10 nm    
42 nm 1.24x ~38 nm 25 nm    
20 nm 0.77x 30 nm   18-26 nm 0.72-0.79x     20 nm 0.71x
70 nm 0.78x 78 nm 1.22x 80 nm 0.80x     90 nm 0.79x
52 nm 0.65x 64 nm 1.00x 64 nm 0.80x     64 nm 0.71x
0.0706 µm² 0.54x 0.080 µm² 0.78x 0.0900 µm² 0.63x     0.090 µm² 0.59x
0.0499 µm² 0.54x 0.064 µm² 0.79x 0.0810 µm² 0.81x     0.081 µm² 0.68x
0.0588 µm² 0.54x                
        0.0174 µm² 0.67x        

Composition

intel 14nm relative density.png
relative percentage of elements on 14nm chip.png

It's important tot note that not all processes compete with each other. The process should cater to the products that will make use of the underlying technology. The composition of the actual integrated circuit also varies by manufacturer and by design due to different goals. For example, the cache on Apple's 14 nm A9 (manufactured by Samsung) accounts almost 1/3 of the entire chip whereas Intel's Broadwell cache accounts for only 10% of the entire chip. Likewise, Intel's Broadwell and Skylake target high-performance and incorporate a large amount of higher-speed elements which are inherently sparse. Tall cells account for almost 30% Skylake's composition and less than 1% on Apple's A8 or A9.

It should be noted that SRAM is the least dense component of the process in a chip, with sometimes up to three or four times less than the density of logic cells that are used in the same process. In recent years, SRAM hasn't scaled as well as logic and I/O have either.

Intel

See also: Intel's Process Technology History

Intel got off to a bumpy start with major yield problems initially, but by Skylake yield has reached very healthy numbers. 14 nm became Intel's 2nd generation FinFET transistors. Intel uses TiN pMOS / TiAlN nMOS as work function metals. Intel makes use of 193 nm immersion lithography with Self-Aligned Double Patterning (SADP) at the critical patterning layers. Compared to all other "14 nm nodes", Intel's process is the densest and considerably so, with >1.5x raw logic density.

Intel's 14 nm process has gone through multiple refinements optimizing higher clock speed, higher drive current, and lower power dissipation. The original "14nm" was used for their Broadwell and mainstream Skylake processors. They improved on their original process with a second process, "14nm+", offering 12% higher drive current at lower power. That process has been used for both Kaby Lake and Server/HEDT Skylake SP/X processors.

A third improved process, "14nm++", is set to begin in late 2017 and will further allow for +23-24% higher drive current for 52% less power vs the original 14nm process. The 14nm++ process also appear to have slightly relaxed poly pitch of 84 nm (from 70 nm). It's unknown what impact, if any, this will have on the density.

intel 14nm gate.png

IBM

IBM developed their own "14HP" (14nm High-Performance) process at their East Fishkill, NY plant. Note that the plant AND the process, along with numerous semiconductor technology IPs, were sold to GlobalFoundries in late 2014. GF still operates the plant (also by ex-IBM semicondcutor engineers) and the process which is used by IBM for their various processors. This process was designed by IBM for their very large chips with effective power supply and clock distribution capable of producing dies as large as 700 mm² and larger with a hierarchical BEOL of 17 levels of copper interconnect for high performance wire-ability. It should be noted that GlobalFoundries had no such capabilities prior to their acquisition of IBM's plant, semiconductor manufacturing group, and IP portfolio.

IBM's HP 14nm CMOS process features a FinFET architecture on an SOI substrate. The use of SOI with FinFet gives IBM a number of unique advantages such as lower parasitic capacitance at the base of the fin as well as simplifies patterning of the active fins and minimizes their variability such as height and thickness. The architecture also includes high-density deep-trench embedded DRAM cells with a reported size of 0.0174 µm². The process features an Lgate of 20nm and smaller (18nm to 27nm) which IBM reported to result in over 35% performance gain verses their HP 22nm process (for identical Vdd = 0.8 V).

Samsung

This process became Samsungs' and GlobalFoundries first generation of FinFET-based transistors. Samsung uses TiN pMOS / TiAIC nMOS as work function metals.

Find models

Click to browse all 14 nm MPU models

14 nm Microprocessors

  • Intel
  • AMD

This list is incomplete; you can help by expanding it.

14 nm Microarchitectures

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Documents

References

  • Natarajan, S., et al. "A 14nm logic technology featuring 2 nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm 2 SRAM cell size." Electron Devices Meeting (IEDM), 2014 IEEE International. IEEE, 2014.
  • Lin, C. H., et al. "High performance 14nm SOI FinFET CMOS technology with 0.0174 µm 2 embedded DRAM and 15 levels of Cu metallization." Electron Devices Meeting (IEDM), 2014 IEEE International. IEEE, 2014.
  • Jan, C-H., et al. "A 14 nm SoC platform technology featuring 2 nd generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um 2 SRAM cells, optimized for low power, high performance and high density SoC products." VLSI Technology (VLSI Technology), 2015 Symposium on. IEEE, 2015.
  • Song, Taejoong, et al. "A 14 nm FinFET 128 Mb SRAM With VMIN Enhancement Techniques for Low-Power Applications." IEEE Journal of Solid-State Circuits 50.1 (2015): 158-169.
  • Weber, Olivier, et al. "14nm FDSOI technology for high speed and energy efficient applications." VLSI Technology (VLSI-Technology): Digest of Technical Papers, 2014 Symposium on. IEEE, 2014.