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Editing 10 nm lithography process
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{{see also|intel/process|l1=Intel's Process Technology History}} | {{see also|intel/process|l1=Intel's Process Technology History}} | ||
[[File:intel 10nm fin.png|right|200px]] | [[File:intel 10nm fin.png|right|200px]] | ||
− | Announced during Intel's Technology and Manufacturing Day 2017, Intel's 10 nm process (P1274) is Intel's | + | Announced during Intel's Technology and Manufacturing Day 2017, Intel's 10 nm process (P1274) is Intel's frist high-volume manufacturing process to employ [[Self-Aligned Quad Patterning]] (SAQP) with production starting in the second half of 2017. Intel detailed {{intel|Hyper-Scaling}}, a marketing term for a suite of techniques used to [[transistor scaling|scale a transistor]], SAQP, a single dummy gate and [[contact over active gate]] (COAG). Intel's initial 10 nm process has up to 60% lower power and 25% better performance than their initial 14 nm but will actually have lower performance than their "14nm++" process. Intel expect their "10nm+" process to surpass that. |
Intel's 10nm process is roughly 1.7x the raw logic density of the next densest 10nm process, albeit due to aggressive pattering techniques they also have the most complex process available to date. The process can support multiple threshold voltages, and features 12-metal interconnect layers with the bottom two made of cobalt. This is the first time cobalt is used in a high volume production node. Because of the ever shrinking geometries the wires get smaller each node. | Intel's 10nm process is roughly 1.7x the raw logic density of the next densest 10nm process, albeit due to aggressive pattering techniques they also have the most complex process available to date. The process can support multiple threshold voltages, and features 12-metal interconnect layers with the bottom two made of cobalt. This is the first time cobalt is used in a high volume production node. Because of the ever shrinking geometries the wires get smaller each node. |