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Difference between revisions of "10 µm lithography process"

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{{lithography processes}}
 
{{lithography processes}}
The '''10 µm lithography process''' was the [[semiconductor process]] technology used by the major semiconductor companies during the years of 1967 and 1973. The typical [[wafer]] size for this process at companies such as [[Fairchild]] and [[TI]] were 1.5 inch (38 mm).
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The '''10 µm lithography process''' was the [[semiconductor process]] technology used by the major semiconductor companies during the years of 1967 and 1973. This process had an effective channel length of roughly 10 µm between the source and drain (Poly-SI channel implant). The typical [[wafer size]] for this process at companies such as [[Fairchild]] and [[TI]] was 2-inch (51 mm).
  
 
== Industry ==
 
== Industry ==
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  |Metal Layers
 
  |Metal Layers
 
  |Technology
 
  |Technology
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|Wafer
 
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{{scrolling table/mid}}
 
|-
 
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! [[Intel]] !! [[TI]] !! [[RCA]] !! [[Fairchild]]
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! [[Intel]] !! [[TI]] !! [[RCA]] !! [[Fairchild]] !! [[National Semiconductor|National]]!! [[microsystems international|MIL]]
 
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| 1970 || 1969 || 1969 ||
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| 1970 || 1969 || 1969 || || || 1969
 
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| ? nm  || ? nm || ? nm  || ? nm  
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| ? nm  || ? nm || ? nm  || ? nm || ? nm || ? nm
 
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| ? nm  || ? nm || ? nm  || ? nm  
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| ? nm  || ? nm || ? nm  || ? nm || ? nm || ? nm
 
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| 2 || 2 || 2 || 2
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| 2 || 2 || 2 || 2 || ||
 
|-
 
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| PMOS || PMOS || PMOS || PMOS
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| PMOS || PMOS || CMOS || PMOS || PMOS ||
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| 51 mm || || || || ||
 
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== 10 µm Microprocessors ==
 
== 10 µm Microprocessors ==
 
* Intel
 
* Intel
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** {{intel|MCS-40|4040}}
 
** {{intel|MCS-40|4040}}
 
** {{intel|MCS-8|8008}}
 
** {{intel|MCS-8|8008}}
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* National
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** {{national|IMP-4}}
 
{{expand list}}
 
{{expand list}}
  
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== 10 µm Chips ==
 
== 10 µm Chips ==
 
* Intel
 
* Intel
** {{intel|1103}}, 1k DRAM, worlds first commercial DRAM
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** {{intel|3000}}
 
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* RCA
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** {{rca|CD4000|CD4000 Series}}
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{{expand list}}
  
  
 
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{{stub}}
[[Category:Lithography]]
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[[category:lithography]]

Latest revision as of 23:04, 20 May 2018

The 10 µm lithography process was the semiconductor process technology used by the major semiconductor companies during the years of 1967 and 1973. This process had an effective channel length of roughly 10 µm between the source and drain (Poly-SI channel implant). The typical wafer size for this process at companies such as Fairchild and TI was 2-inch (51 mm).

Industry[edit]

Fab
Process Name​
1st Production​
Contacted Gate Pitch​
Interconnect Pitch​
Metal Layers​
Technology​
Wafer
Intel TI RCA Fairchild National MIL
 
1970 1969 1969 1969
 ? nm  ? nm  ? nm  ? nm  ? nm  ? nm
 ? nm  ? nm  ? nm  ? nm  ? nm  ? nm
2 2 2 2
PMOS PMOS CMOS PMOS PMOS
51 mm

10 µm Microprocessors[edit]

This list is incomplete; you can help by expanding it.


Click to browse all 10 µm models

10 µm Chips[edit]

This list is incomplete; you can help by expanding it.


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