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1.5 µm lithography process
Revision as of 17:40, 28 June 2017 by David (talk | contribs) (1.5 µm Microarchitectures)

The 1.5 µm lithography process was the semiconductor process technology used by the major semiconductor companies in the mid 1980s. This process had an effective channel length of roughly 1.5 µm between the source and drain. By the late 80s this process was replaced by 1.3 µm, 1.2 µm, and 1 µm processes.

Industry

Fab
Process Name​
1st Production​
Contacted Gate Pitch​
Interconnect Pitch (M1P)​
Metal Layers​​
SRAM bit cell​
Wafer
Intel Intel Intel HP AMD DEC
HMOS-II HMOS-E P646 (CHMOS III) NMOS III CMOS-2
1982 1982 1985 1981 1982
 ? nm  ? nm  ? nm 1.5 µm
 ? nm  ? nm  ? nm 2.5 µm
2  ? 2 2 2 2
 ? µm²  ? µm²  ? µm²  ? µm²  ? µm²
125 mm 150 mm

HP

DEC

DEC operated their 1.5 µm process (CMOS-2) at their Hudson foundry. This 2 ML process had an effective channel length of 0.9 µm with a polycide width of 1.5 µm (1.5 µm spacing) and a TOX of 22.5 nm.

1.5 µm Microprocessors

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1.5 µm Microarchitectures

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