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Difference between revisions of "1.5 µm lithography process"

(1.5 µm Microarchitectures)
(Industry)
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|-
 
|-
! [[Intel]] || [[Intel]]  || [[Intel]] || [[HP]] || [[AMD]]
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! [[Intel]] || [[Intel]]  || [[Intel]] || [[HP]] || [[AMD]] || [[DEC]]
 
|- style="text-align: center;"
 
|- style="text-align: center;"
| HMOS-II || HMOS-E || P646 (CHMOS III) || NMOS III ||  
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| HMOS-II || HMOS-E || P646 (CHMOS III) || NMOS III || || CMOS-2
 
|- style="text-align: center;"
 
|- style="text-align: center;"
| 1982 || 1982 || 1985 || 1981 || 1982
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| 1982 || 1982 || 1985 || 1981 || 1982 ||
 
|-
 
|-
| ? nm || ? nm  || ? nm  || 1.5 µm ||
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| ? nm || ? nm  || ? nm  || 1.5 µm || ||
 
|-
 
|-
| ? nm ||  ? nm || ? nm || 2.5 µm ||
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| ? nm ||  ? nm || ? nm || 2.5 µm || ||
 
|-
 
|-
| 2 || ? || 2 || 2 || 2  
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| 2 || ? || 2 || 2 || 2 || 2
 
|-
 
|-
| ? µm<sup>2</sup> ||  ? µm<sup>2</sup> ||  ? µm<sup>2</sup> || ? µm<sup>2</sup> || ? µm<sup>2</sup>
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| ? µm² ||  ? µm² ||  ? µm² || ? µm² || ? µm² ||
 
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| 125 mm  || || 150 mm  ||  ||
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| 125 mm  || || 150 mm  ||  || ||
 
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Revision as of 14:35, 11 June 2017

The 1.5 µm lithography process was the semiconductor process technology used by the major semiconductor companies in the mid 1980s. This process had an effective channel length of roughly 1.5 µm between the source and drain. By the late 80s this process was replaced by 1.3 µm, 1.2 µm, and 1 µm processes.

Industry

Fab
Process Name​
1st Production​
Contacted Gate Pitch​
Interconnect Pitch (M1P)​
Metal Layers​​
SRAM bit cell​
Wafer
Intel Intel Intel HP AMD DEC
HMOS-II HMOS-E P646 (CHMOS III) NMOS III CMOS-2
1982 1982 1985 1981 1982
 ? nm  ? nm  ? nm 1.5 µm
 ? nm  ? nm  ? nm 2.5 µm
2  ? 2 2 2 2
 ? µm²  ? µm²  ? µm²  ? µm²  ? µm²
125 mm 150 mm

Design Rules

1.5 µm Microprocessors

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1.5 µm Microarchitectures

This list is incomplete; you can help by expanding it.