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EPYC 7252P
General Info
Designer	AMD
Manufacturer	TSMC, GlobalFoundries
Model Number	7252P
Part Number	100-000000081
Market	Server
Introduction	August 7, 2019 (announced) August 7, 2019 (launched)
Shop	Amazon
General Specs
Family	EPYC
Series	7002
Locked	Yes
Frequency	2,800 MHz
Turbo Frequency	3,200 MHz
Clock multiplier	28
Microarchitecture
ISA	x86-64 (x86)
Microarchitecture	Zen 2
Core Name	Rome
Core Family	23
Process	7 nm, 14 nm
Technology	CMOS
MCP	Yes (3 dies)
Word Size	64 bit
Cores	8
Threads	16
Max Memory	4 TiB
Multiprocessing
Max SMP	1-Way (Uniprocessor)
Electrical
TDP	120 W
Packaging
Package	SP3, FCLGA-4094 (FC-OLGA)
Dimension	75.4 mm × 58.5 mm × 6.26 mm
Pitch	0.87 mm × 1 mm
Contacts	4094
Socket	SP3, LGA-4094

EPYC 7252P is a 64-bit octa-core x86 server microprocessor designed and introduced by AMD in mid-2019. This multi-chip processor, which is based on the Zen 2 microarchitecture, incorporates logic fabricated TSMC 7 nm process and I/O fabricated on GlobalFoundries 14 nm process. The 7252P has a TDP of 120 W with a base frequency of 2.8 GHz and a boost frequency of up to 3.2 GHz. This processor supports single-socket configurations only and up to 4 TiB of eight channels DDR4-3200 memory per socket.

Cache

Main article: Zen 2 § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 512 KiB 524,288 B 0.5 MiB L1I$ 256 KiB 262,144 B 0.25 MiB 8x32 KiB 8-way set associative   L1D$ 256 KiB 262,144 B 0.25 MiB 8x32 KiB 8-way set associative   L2$ 4 MiB 4,096 KiB 4,194,304 B 0.00391 GiB     8x512 KiB 8-way set associative write-back L3$ 64 MiB 65,536 KiB 67,108,864 B 0.0625 GiB     4x16 MiB

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR4-3200 Supports ECC Yes Max Mem 4 TiB Controllers 8 Channels 8 Max Bandwidth 190.7 GiB/s 195,276.8 MiB/s 204.763 GB/s 204,762.566 MB/s 0.186 TiB/s 0.205 TB/s Bandwidth Single 23.84 GiB/s Double 47.68 GiB/s Quad 95.37 GiB/s Hexa 143.1 GiB/s Octa 190.7 GiB/s