From WikiChip
Xeon W-2150B - Intel
| Edit Values | |
| Xeon W-2150B | |
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| Frox | |
| 200px | |
| General Info | |
| Designer | Intel |
| Manufacturer | Intel |
| Model Number | W-2150B |
| Part Number | pEot, qjyM |
| S-Spec | cbNn, HvwW, ZWOv DdqO (QS), rlKK (QS), cAjK (QS) |
| Market | Workstation |
| Introduction | June 5, 2017 (announced) December 21, 2017 (launched) |
| End-of-life | DEMU (last order) NQEl (last shipment) |
| Release Price | NTyu PlQs (tray) VeAI (box) |
| Shop | Amazon |
| General Specs | |
| Family | Xeon W, hLcv |
| Series | W-2000 |
| Locked | crQO |
| Frequency | 3,000 MHz, bwBp |
| Turbo Frequency | vUnd |
| Turbo Frequency | 4,500 MHz (1 core), 4,500 MHz (2 cores), 4,300 MHz (3 cores), 4,100 MHz (5 cores), 4,100 MHz (6 cores), 4,100 MHz (8 cores), 3,800 MHz (9 cores), LquS (11 cores), ITOG (12 cores), Bytc (14 cores), YafF (15 cores), PzRf (17 cores), YojI (18 cores), ffDz (20 cores), FRWB (21 cores), RRhJ (23 cores), zFqq (24 cores), yKuP (26 cores), EGDC (27 cores), pRBy (29 cores), hyXR (30 cores), Xzlx (32 cores) |
| Bus type | DMI 3.0 |
| Bus speed | xxnv |
| Bus rate | 4 × 8 GT/s |
| Clock multiplier | 30 |
| CPUID | xOoQ, FmBz, gHGB |
| Neuromorphic Specs | |
| Neurons | kTsq |
| Synapses | hxyt |
| Microarchitecture | |
| ISA | x86-64 |
| Microarchitecture | Skylake (server), bygc |
| Platform | Basin Falls |
| Chipset | FFfU, BVLj |
| Core Name | Skylake W, dgeX |
| Core Family | 6, bWeV |
| Core Model | CUoC, pQDz |
| Core Stepping | U0, fQLH |
| Process | 14 nm, rycs |
| Transistors | EiHY |
| Technology | CMOS |
| Die | CXka |
| MCP | qgrV |
| Word Size | 64 bit |
| Cores | 10 |
| Threads | 20 |
| Max Memory | 512 GiB |
| Max Address Mem | pyjF |
| Multiprocessing | |
| Max SMP | 1-Way (Uniprocessor) |
| Interconnect | wCCQ |
| Interconnect Links | DZlW |
| Interconnect Rate | kRoD |
| Electrical | |
| Power dissipation | MbBx |
| Power dissipation (average) | HuDI |
| Power (idle) | KyzP |
| Vcore | sEVK ± yjDZ |
| Vcore | ffCE-unsi |
| VI/O | Lapn ± ylNg |
| SDP | Ysbp |
| TDP | GAEz, VsUK |
| TDP (Typical) | EojP |
| cTDP down | SPIZ |
| cTDP down frequency | VBrU |
| cTDP up | ezNP |
| cTDP up frequency | WkKt |
| OP Temperature | chAo – Fjxl |
| Tjunction | pRbF – tvyP |
| Tcase | YfiB – qKWG |
| Tstorage | daaY – PnFG |
| Tambient | POtl – RXqr |
| TDTS | fYRz – cMLv |
| Packaging | |
| Unknown package "Lgom" | |
| wViU | |
| Jpyv | |
| Succession | |
| Contemporary | |
| pipL | |
W-2150B is a 64-bit deca-core x86 enterprise performance workstation microprocessor introduced by Intel in 2017.
- This processors, which is fabricated on an enhanced 14nm+ process based on the Skylake server microarchitecture,
- operates at 3.0 GHz with a TDP of 120 W and a turbo boost frequency of up to 4.5 GHz.
- This chip supports up to 512 GiB of quad-channel DDR4-2666 ECC memory.
- This specific model appears to be a special model for Apple for their iMac Pro.
Cache
- Main article: Skylake § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
Expansion Options |
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Features
[Edit/Modify Supported Features]
Frequencies
- See also: Intel's CPU Frequency Behavior
| Mode | Base | Turbo Frequency/Active Cores | |||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | ||
| Normal | 3,000 MHz | 4,500 MHz | 4,500 MHz | 4,300 MHz | 4,300 MHz | 4,100 MHz | 4,100 MHz | 4,100 MHz | 4,100 MHz | 3,800 MHz | 3,800 MHz |
| AVX2 | 4,000 MHz | 4,000 MHz | 3,800 MHz | 3,800 MHz | 3,700 MHz | 3,700 MHz | 3,700 MHz | 3,700 MHz | 3,400 MHz | 3,400 MHz | |
| AVX512 | 4,000 MHz | 4,000 MHz | 3,800 MHz | 3,800 MHz | 3,200 MHz | 3,200 MHz | 3,200 MHz | 3,200 MHz | 3,000 MHz | 3,000 MHz | |
Facts about "Xeon W-2150B - Intel"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon W-2150B - Intel#pcie + |
| back image | File:rbDg + |
| base frequency | 3,000 MHz (3 GHz, 3,000,000 kHz) + |
| bus links | 4 + |
| bus rate | 8,000 MT/s (8 GT/s, 8,000,000 kT/s) + |
| bus type | DMI 3.0 + |
| chipset | FFfU + and BVLj + |
| clock multiplier | 30 + |
| core count | 10 + |
| core family | 6 + and bWeV + |
| core model | CUoC + and pQDz + |
| core name | Skylake W + and dgeX + |
| core stepping | U0 + and fQLH + |
| core voltage tolerance | yjDZ + |
| cpuid | xOoQ +, FmBz + and gHGB + |
| designer | Intel + |
| family | Xeon W + and hLcv + |
| first announced | June 5, 2017 + |
| first launched | December 21, 2017 + |
| full page name | intel/xeon w/w-2150b + |
| has advanced vector extensions | true + |
| has advanced vector extensions 2 | true + |
| has advanced vector extensions 512 | true + |
| has ecc memory support | true + |
| has extended page tables support | true + |
| has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions +, Memory Protection Extensions +, Secure Key Technology +, OS Guard + and Identity Protection Technology + |
| has intel enhanced speedstep technology | true + |
| has intel identity protection technology support | true + |
| has intel secure key technology | true + |
| has intel speed shift technology | true + |
| has intel supervisor mode execution protection | true + |
| has intel trusted execution technology | true + |
| has intel turbo boost technology 2 0 | true + |
| has intel vpro technology | true + |
| has intel vt-d technology | true + |
| has intel vt-x technology | true + |
| has second level address translation support | true + |
| has simultaneous multithreading | true + |
| has transactional synchronization extensions | true + |
| has x86 advanced encryption standard instruction set extension | true + |
| io voltage tolerance | ylNg + |
| isa | x86-64 + |
| l1$ size | 640 KiB (655,360 B, 0.625 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 320 KiB (327,680 B, 0.313 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 320 KiB (327,680 B, 0.313 MiB) + |
| l2$ description | 16-way set associative + |
| l2$ size | 10 MiB (10,240 KiB, 10,485,760 B, 0.00977 GiB) + |
| l3$ description | 11-way set associative + |
| l3$ size | 13.75 MiB (14,080 KiB, 14,417,920 B, 0.0134 GiB) + |
| ldate | December 21, 2017 + |
| main image | |
| main image caption | Frox + |
| manufacturer | Intel + |
| market segment | Workstation + |
| max cpu count | 1 + |
| max dts temperature | cMLv + |
| max memory | 524,288 MiB (536,870,912 KiB, 549,755,813,888 B, 512 GiB, 0.5 TiB) + |
| max memory address | pyjF + |
| max memory bandwidth | 79.47 GiB/s (81,377.28 MiB/s, 85.33 GB/s, 85,330.263 MB/s, 0.0776 TiB/s, 0.0853 TB/s) + |
| max memory channels | 4 + |
| max operating temperature | Fjxl + |
| microarchitecture | Skylake (server) + and bygc + |
| min dts temperature | fYRz + |
| min operating temperature | chAo + |
| model number | W-2150B + |
| name | Xeon W-2150B + |
| neuron count | kTsq + |
| number of avx-512 execution units | 2 + |
| part number | pEot + and qjyM + |
| platform | Basin Falls + |
| process | 14 nm (0.014 μm, 1.4e-5 mm) + |
| s-spec | cbNn +, HvwW + and ZWOv + |
| s-spec (qs) | DdqO +, rlKK + and cAjK + |
| series | W-2000 + |
| smp interconnect | wCCQ + |
| smp interconnect links | DZlW + |
| smp interconnect rate | kRoD + |
| smp max ways | 1 + |
| supported memory type | DDR4-2666 + |
| synapse count | hxyt + |
| technology | CMOS + |
| thread count | 20 + |
| turbo frequency (17 cores) | PzRf + |
| turbo frequency (18 cores) | YojI + |
| turbo frequency (1 core) | 4,500 MHz (4.5 GHz, 4,500,000 kHz) + |
| turbo frequency (20 cores) | ffDz + |
| turbo frequency (21 cores) | FRWB + |
| turbo frequency (23 cores) | RRhJ + |
| turbo frequency (24 cores) | zFqq + |
| turbo frequency (26 cores) | yKuP + |
| turbo frequency (27 cores) | EGDC + |
| turbo frequency (29 cores) | pRBy + |
| turbo frequency (2 cores) | 4,500 MHz (4.5 GHz, 4,500,000 kHz) + |
| turbo frequency (30 cores) | hyXR + |
| turbo frequency (32 cores) | Xzlx + |
| turbo frequency (3 cores) | 4,300 MHz (4.3 GHz, 4,300,000 kHz) + |
| turbo frequency (5 cores) | 4,100 MHz (4.1 GHz, 4,100,000 kHz) + |
| turbo frequency (6 cores) | 4,100 MHz (4.1 GHz, 4,100,000 kHz) + |
| turbo frequency (8 cores) | 4,100 MHz (4.1 GHz, 4,100,000 kHz) + |
| turbo frequency (9 cores) | 3,800 MHz (3.8 GHz, 3,800,000 kHz) + |
| word size | 64 bit (8 octets, 16 nibbles) + |
| x86/has memory protection extensions | true + |
