• amd/am186cx/am186ch-25ki\w
  | irq lines = 36 | io lines = 48
  4 KB (378 words) - 16:50, 30 June 2017
• amd/am186cx/am186ch-40ki\w
  | irq lines = 36 | io lines = 48
  4 KB (378 words) - 16:51, 30 June 2017
• amd/am186cx/am186cc-25kc\w
  | irq lines = 36 | io lines = 48
  4 KB (390 words) - 16:49, 30 June 2017
• amd/am186cx/am186cc-40kc\w
  | irq lines = 36 | io lines = 48
  4 KB (390 words) - 16:50, 30 June 2017
• amd/am186cx/am186cc-50kc\w
  | irq lines = 36 | io lines = 48
  4 KB (390 words) - 16:50, 30 June 2017
• amd/am186cx/am186cc-25ki\w
  | irq lines = 36 | io lines = 48
  4 KB (402 words) - 16:50, 30 June 2017
• amd/am186cx/am186cc-40ki\w
  | irq lines = 36 | io lines = 48
  4 KB (402 words) - 16:50, 30 June 2017
• amd/microarchitectures/zen
  ** Large μop cache (2K instructions) * Cache system
  79 KB (12,095 words) - 15:27, 9 June 2023
• amd/microarchitectures/zen 2
  *** Improved µOP cache tags *** Improved µOP cache
  57 KB (8,701 words) - 22:11, 9 October 2022
• intel/microarchitectures/gen9.5
  ...vels of performance. Some models also support an additional [[eDRAM]] side cache. ...ontains 2 slices with 48 execution units. Has an additional [[eDRAM]] side cache.
  29 KB (3,752 words) - 13:14, 19 April 2023
• intel/microarchitectures/gen9
  ...vels of performance. Some models also support an additional [[eDRAM]] side cache. ...ontains 2 slices with 48 execution units. Has an additional [[eDRAM]] side cache.
  33 KB (4,255 words) - 17:41, 1 November 2018
• ibm/microarchitectures/power9
  * Cache * Cache
  14 KB (1,905 words) - 23:38, 22 May 2020
• qualcomm/microarchitectures/falkor
  * L0I Cache: ** 64-byte lines
  6 KB (822 words) - 13:01, 19 May 2021
• arm/history
  ...d [[Steve Furber]] designed a reference model in [[BBC BASIC]] in just 808 lines of code. The first processor, the {{armh|ARM1}}, was fabricated on [[VLSI T ...e improvements through a [[process shrink]] and the introduction of on-die cache. Thanks to those improvements, the processor was now capable of running at
  6 KB (834 words) - 01:12, 29 January 2019
• loongson/godson 2/2h
  == Cache == {{main|loongson/microarchitectures/GS464V#Memory_Hierarchy|l1=GS464V § Cache}}
  5 KB (591 words) - 16:31, 13 December 2017
• acorn/microarchitectures/arm3
  ...the {{\\|ARM2}} with higher performance through the introduction of on-die cache but without any major changes to the core itself. The ARM3 was designed by ...ely impact the overall cost. Instead, the design team opted to integrating cache.
  7 KB (1,035 words) - 06:24, 21 November 2023
• arm holdings/microarchitectures/arm6
  * Cache ** L1 Cache (unified)
  11 KB (1,679 words) - 21:00, 15 May 2024
• intel/microarchitectures/skylake (server)
  ...LFLUSHOPT</code>}} - Flush & Invalidates memory operand and its associated cache line (All L1/L2/L3 etc..) * {{x86|CLWB|<code>CLWB</code>}} - Force cache line write-back without flush
  52 KB (7,651 words) - 00:59, 6 July 2022
• intel/upgrade service
  ! Model !! Frequency !! Cache !! Model !! Frequency !! Cache ...ices without compromising pricing of their mainstream and high-end product lines. Upgrade Service was designed for low-end models that were mostly used excl
  4 KB (545 words) - 12:49, 18 July 2020
• cavium/microarchitectures/vulcan
  *** Half L2 Cache Size (256 KiB, down form 512 KiB) * Cache
  17 KB (2,449 words) - 22:11, 4 October 2019

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