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- |predecessor link=intel/cores/arrandale |successor link=intel/cores/ivy bridge m3 KB (489 words) - 15:57, 4 September 2017
- |predecessor link=intel/cores/avoton |successor link=intel/cores/elkhart_lake7 KB (950 words) - 06:47, 25 April 2020
- |cores=1 |cores 2=411 KB (1,613 words) - 08:39, 3 March 2024
- |cores=2 |cores 2=432 KB (4,535 words) - 12:12, 24 September 2024
- |cores=4 |extension 20=VT-x5 KB (650 words) - 03:47, 9 January 2020
- |predecessor link=intel/cores/coffee lake s |successor link=intel/cores/comet lake s4 KB (523 words) - 01:38, 7 May 2019
- |predecessor link=intel/cores/broadwell de |successor link=intel/cores/hewitt lake6 KB (774 words) - 01:49, 25 February 2019
- |frequency=2,000 MHz |turbo frequency1=3,000 MHz5 KB (729 words) - 05:20, 24 March 2023
- {{see also|amd/cores/great_horned_owl|amd/microarchitectures/zen|l1=Great Horned Owl|l2=Zen µar ...|L3$|%TDP|T<sub>jmin</sub>|T<sub>jmax</sub>|%Base|%Turbo (Max)|Memory|Name|Frequency}}11 KB (1,642 words) - 03:53, 2 January 2021
- |cores=8 |cores 2=108 KB (978 words) - 18:41, 26 March 2024
- |frequency=2314 MHz |frequency 2=1690 MHz5 KB (713 words) - 07:19, 16 May 2024
- |cores=2 |extension 20=VT-x4 KB (565 words) - 09:03, 24 May 2019
- |cores=4 |extension 20=VT-x10 KB (1,357 words) - 18:48, 13 September 2022
- |predecessor link=intel/cores/kaby lake dt |successor link=intel/cores/coffee_lake_er5 KB (748 words) - 12:14, 2 June 2019
- ...;GB/s in each direction.<!--Beck2018, Naffziger2020, EPYC Tech Day 2017-06-20--> {{comp table header|cols|Cores|Threads|L2$|L3$|Base|Turbo|Memory|{{abbr|TDP}}|Launched|Price|{{abbr|OPN}}}}86 KB (17,313 words) - 02:48, 13 March 2023
- |frequency=2,400 MHz |turbo frequency1=3,900 MHz5 KB (820 words) - 02:38, 29 December 2019
- |predecessor link=intel/cores/coffee lake h |successor link=intel/cores/comet lake h4 KB (507 words) - 07:45, 5 May 2019
- |successor link=intel/cores/hewitt lake * '''TDP:''' 20-65 W6 KB (784 words) - 08:28, 10 January 2022
- |frequency=2,300 MHz |turbo frequency1=3,100 MHz4 KB (655 words) - 05:17, 9 April 2022
- |predecessor link=intel/cores/coffee_lake_e ...C246). The microprocessor is connected to the chipset via 4 of the chip's 20 PCIe lanes using Intel's proprietary {{intel|Direct Media Interface}} 3.0 (5 KB (721 words) - 12:41, 12 June 2023