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- | package module 1 = {{packages/intel/bga-1288}}4 KB (559 words) - 16:19, 13 December 2017
- | package module 1 = {{packages/intel/bga-1288}}5 KB (570 words) - 16:22, 13 December 2017
- | socket = BGA-1521 | socket 2 = BGA-86811 KB (1,489 words) - 09:25, 30 December 2020
- | package 0 = BGA-350 | package 0 type = BGA4 KB (438 words) - 16:10, 13 December 2017
- | package 0 = BGA-350 | package 0 type = BGA4 KB (438 words) - 16:10, 13 December 2017
- | package 0 = BGA-350 | package 0 type = BGA4 KB (438 words) - 16:10, 13 December 2017
- | package 0 = BGA-350 | package 0 type = BGA4 KB (422 words) - 16:10, 13 December 2017
- | package 0 = BGA-350 | package 0 type = BGA4 KB (422 words) - 16:10, 13 December 2017
- | package 0 = BGA-350 | package 0 type = BGA4 KB (422 words) - 16:10, 13 December 2017
- | package 0 = BGA-525 | package 0 type = BGA4 KB (465 words) - 16:10, 13 December 2017
- | package 0 = BGA-525 | package 0 type = BGA4 KB (465 words) - 16:10, 13 December 2017
- | package 0 = BGA-525 | package 0 type = BGA4 KB (465 words) - 16:10, 13 December 2017
- | package 0 = BGA-525 | package 0 type = BGA4 KB (449 words) - 16:10, 13 December 2017
- | package 0 = BGA-525 | package 0 type = BGA4 KB (449 words) - 16:10, 13 December 2017
- | package 0 = BGA-525 | package 0 type = BGA4 KB (449 words) - 16:10, 13 December 2017
- | socket = BGA-15216 KB (827 words) - 15:41, 29 December 2016
- |socket=BGA-1515 ...allowing for 4 GT/s transfer rate. KBL-Y chips use {{intel|BGA-1515|Socket BGA-1515}}.4 KB (594 words) - 06:30, 6 April 2019
- ...GT/s transfer rate. All Kaby Lake U processors use {{intel|BGA-1356|Socket BGA-1356}} and all Iris models include 64 MiB of side cache.6 KB (820 words) - 14:10, 29 February 2020
- |socket=BGA-1440 ...roprocessor]] and the [[chipset]]. Kaby Lake H are {{intel|BGA-1440|Socket BGA-1440}} and use {{intel|Union Point}} chipset ({{intel|Platform Controller H5 KB (699 words) - 13:43, 8 April 2018
- | socket 0 = BGA-452 | socket 0 type = BGA4 KB (461 words) - 16:31, 13 December 2017