• amd/am9080
  This table is generated automatically from the data in the actual articles. | {{\|Am8228}} || system controller & bus driver
  5 KB (683 words) - 23:46, 7 March 2018
• intel/mcs-8/isa
  | data size = 8 bit This ISA has an {{arch|8}} data and address bus. This architecture included seven 8-bit registers, 48 instructions, and int
  13 KB (2,079 words) - 21:48, 17 September 2024
• intel/microarchitectures/bonnell
  ...MT/s dual mode ([[gunning transceiver logic|GTL]] & [[CMOS]]) [[front side bus|FSB]] ** L1 Data Cache
  38 KB (5,468 words) - 20:29, 23 May 2019
• intel/microarchitectures/silvermont
  * {{x86|PREFETCHW|<code>PREFETCHW</code>}} - Prefetch data into caches, hinting a write is expected in the future ...by integrating and other support chips on-die, it still used a Front Side Bus implementation to talk to North Bridge. In Silvermont, this was replaced wi
  9 KB (1,160 words) - 09:35, 25 September 2019
• intel/pentium (2009)
  ...essors are [[dual-core]] processors. These processors had the [[front-side bus|FSB]] replaced with {{intel|Direct Media Interface}} 1.0. These processors * '''Bus:''' {{intel|DMI}} (2.5 GT/s) interface
  20 KB (2,661 words) - 00:45, 11 October 2017
• intel/celeron
  ...essors are [[dual-core]] processors. These processors had the [[front-side bus|FSB]] replaced with {{intel|Direct Media Interface}} 1.0. These processors * '''Bus:''' {{intel|DMI}} (2.5 GT/s) interface
  25 KB (3,201 words) - 03:13, 22 September 2018
• intel/microarchitectures/sandy bridge (client)
  ** New SVID (Serial Voltage ID bus) ...sists of dedicated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a unified L2 TLB (STLB).
  84 KB (13,075 words) - 00:54, 29 December 2020
• intel/microarchitectures/skylake (client)
  ** Bus/Interface to Chipset ...sists of dedicated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a unified L2 TLB (STLB).
  79 KB (11,922 words) - 06:46, 11 November 2022
• intel/microarchitectures/kaby lake
  ...sists of dedicated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a unified L2 TLB (STLB). ...} are a two-chip solution linked together via Intel's standard [[DMI 3.0]] bus interface which utilizes 4 of the CPU's 20 [[PCIe]] 3.0 lanes (having a tra
  38 KB (5,431 words) - 10:41, 8 April 2024
• intel/microarchitectures/ice lake (client)
  ** 1.4x higher data rates (3733 MT/s, up from 2666 MT/s) ...nit in the processor. All clock domains are some multiple of the [virtual] bus clock ([[BCLK]]).
  23 KB (3,613 words) - 12:31, 20 June 2021
• intel/mobile pentium ii
  ...l keeping everything closely tied together with respect to the [[back-side bus]]. The separate (slower) cache die also meant the processor was cheaper to This table is generated automatically from the data in the actual articles.
  5 KB (635 words) - 09:54, 11 November 2017
• intel/80386
  ! Model !! Introduction !! Ext. Bus !! Frequency !! Notes ! Model !! Introduction !! Ext. Bus !! Frequency !! Notes
  4 KB (400 words) - 08:43, 5 December 2022
• intel/80486
  ...tly used data and instructions. Various enhancements were also made to the bus interface including faster communication that required single clock cycle i This table is generated automatically from the data in the actual articles.
  8 KB (953 words) - 08:27, 29 October 2022
• intel/80486/486gx-33
  | bus type = FSB | bus speed = 33 MHz
  2 KB (214 words) - 16:13, 13 December 2017
• intel/core i3
  ...essors are [[dual-core]] processors. These processors had the [[front-side bus|FSB]] replaced with {{intel|Direct Media Interface}} 1.0. These processors This table is generated automatically from the data in the actual articles.
  25 KB (3,397 words) - 03:12, 3 October 2022
• intel/core i5
  ...essors are [[dual-core]] processors. These processors had the [[front-side bus|FSB]] replaced with {{intel|Direct Media Interface}} 1.0 and introduced {{x * '''Bus:''' {{intel|DMI}} (2.5 GT/s) interface
  34 KB (4,663 words) - 20:38, 20 February 2023
• amd/am486
  ...versions introduced had lower clock frequency which matched their external bus speed. Later versions introduced a [[clock multiplier]]: DX2 having a multi This table is generated automatically from the data in the actual articles.
  13 KB (1,897 words) - 09:30, 21 July 2021
• amd/am5x86
  ...nce comparable to the Pentium-75. The clock multiplier was set to x4 (e.g. bus speed of 33 MHz would have a core frequency of 133 MHz). Essentially, one c This table is generated automatically from the data in the actual articles.
  7 KB (1,043 words) - 16:50, 14 June 2020
• amd/am286
  This table is generated automatically from the data in the actual articles. <tr><th>Model</th><th>Launched</th><th>Process</th><th>Freq</th><th>Bus</th><th>Max Mem</th><th>Package</th><th>Power</th><th>Min T_case<
  9 KB (1,192 words) - 01:35, 29 May 2016
• amd/am286zx-lx
  ...amd|Am286#Low-power CMOS models|from the Am286 family}} and incorporated a bus controller, DMA controller, interrupt controller, and clock generator. The This table is generated automatically from the data in the actual articles.
  5 KB (750 words) - 21:22, 24 May 2016

View (previous 20 | next 20) (20 | 50 | 100 | 250 | 500)