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Difference between revisions of "arm holdings/microarchitectures/arm6"
(Created page with "{{armh title|ARM6|arch}} {{microarchitecture |atype=CPU |name=ARM6 |designer=ARM Holdings |manufacturer=VLSI Technology |introduction=1993 |process=0.8 µm |cores=1 |type=Scal...") |
(No difference)
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Revision as of 10:14, 2 July 2017
| Edit Values | |
| ARM6 µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | ARM Holdings |
| Manufacturer | VLSI Technology |
| Introduction | 1993 |
| Process | 0.8 µm |
| Core Configs | 1 |
| Pipeline | |
| Type | Scalar, Pipelined |
| Stages | 3 |
| Decode | 1-way |
| Instructions | |
| ISA | ARMv3 |
| Cache | |
| L1 Cache | 4 KiB/core 64-way set associative |
| Succession | |
ARM6 is an ARM microarchitecture designed by ARM Holdings and introduced in 1993 as a successor to the ARM3. This was the first design by ARM as an independent company.
Retrieved from "https://en.wikichip.org/w/index.php?title=arm_holdings/microarchitectures/arm6&oldid=49987"
Facts about "ARM6 - Microarchitectures - ARM"
| codename | ARM6 + |
| core count | 1 + |
| designer | ARM Holdings + |
| first launched | 1993 + |
| full page name | arm holdings/microarchitectures/arm6 + |
| instance of | microarchitecture + |
| instruction set architecture | ARMv3 + |
| manufacturer | VLSI Technology + |
| microarchitecture type | CPU + |
| name | ARM6 + |
| pipeline stages | 3 + |
| process | 800 nm (0.8 μm, 8.0e-4 mm) + |