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Difference between revisions of "intel/core i9/i9-7980xe"
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− | '''Core i9-7980XE''' is a {{arch|64}} [[octadeca-core]] top-of-the-line [[x86]] desktop microprocessor introduced by [[Intel]] in mid-[[2017]]. This chip, which is based on the {{intel|Skylake|l=arch}} microarchitecture, is fabricated on Intel's [[14 nm process]]. The i9-7980XE operates at ? GHz with a TDP of 160 W and a {{intel|Turbo Boost}} frequency of ? GHz. The processor supports up to 128 GiB of quad-channel DDR4-2666 memory. | + | '''Core i9-7980XE''' is a {{arch|64}} [[octadeca-core]] top-of-the-line [[x86]] desktop microprocessor introduced by [[Intel]] in mid-[[2017]]. This chip, which is based on the {{intel|Skylake|l=arch}} microarchitecture, is fabricated on Intel's enhanced [[14 nm process|14nm+ process]]. The i9-7980XE operates at ? GHz with a TDP of 160 W and a {{intel|Turbo Boost}} frequency of ? GHz. The processor supports up to 128 GiB of quad-channel DDR4-2666 memory. |
The Core i9-7980XE succeeds the {{intel|Core i7-6950X}} as Intel's flagship microprocessor based on {{intel|Skylake|l=arch}} microarchitecture - also becoming the first consumer-class octadeca-core microprocessor. | The Core i9-7980XE succeeds the {{intel|Core i7-6950X}} as Intel's flagship microprocessor based on {{intel|Skylake|l=arch}} microarchitecture - also becoming the first consumer-class octadeca-core microprocessor. |
Revision as of 11:48, 16 June 2017
Template:mpu Core i9-7980XE is a 64-bit octadeca-core top-of-the-line x86 desktop microprocessor introduced by Intel in mid-2017. This chip, which is based on the Skylake microarchitecture, is fabricated on Intel's enhanced 14nm+ process. The i9-7980XE operates at ? GHz with a TDP of 160 W and a Turbo Boost frequency of ? GHz. The processor supports up to 128 GiB of quad-channel DDR4-2666 memory.
The Core i9-7980XE succeeds the Core i7-6950X as Intel's flagship microprocessor based on Skylake microarchitecture - also becoming the first consumer-class octadeca-core microprocessor.
Cache
- Main article: Skylake § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
Integrated Memory Controller
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Expansions
Expansion Options
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Graphics
This processor has no integrated graphics.
Features
[Edit/Modify Supported Features]
Facts about "Core i9-7980XE - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Core i9-7980XE - Intel#io + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has ecc memory support | false + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Turbo Boost Technology 2.0 +, Turbo Boost Max Technology 3.0 +, Enhanced SpeedStep Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions +, Memory Protection Extensions + and Software Guard Extensions + |
has intel enhanced speedstep technology | true + |
has intel turbo boost max technology 3 0 | true + |
has intel turbo boost technology 2 0 | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has second level address translation support | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
l1$ size | 1,152 KiB (1,179,648 B, 1.125 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 576 KiB (589,824 B, 0.563 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 576 KiB (589,824 B, 0.563 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 18 MiB (18,432 KiB, 18,874,368 B, 0.0176 GiB) + |
l3$ description | 11-way set associative + |
l3$ size | 24.75 MiB (25,344 KiB, 25,952,256 B, 0.0242 GiB) + |
max memory bandwidth | 79.47 GiB/s (81,377.28 MiB/s, 85.33 GB/s, 85,330.263 MB/s, 0.0776 TiB/s, 0.0853 TB/s) + |
max memory channels | 4 + |
max pcie lanes | 44 + |
supported memory type | DDR4-2666 + |
x86/has memory protection extensions | true + |
x86/has software guard extensions | true + |