Difference between revisions of "hisilicon/kirin/970"

	Edit Values
	Kirin 970
	DQiD
	200px
	General Info
Designer	HiSilicon
Manufacturer	TSMC
Model Number	970
Part Number	Hi3670,; MmUF
S-Spec	lMwI, tVlW, LtUw; xZFB (QS), VuXx (QS), ZIdP (QS)
Market	Mobile
Introduction	September 1, 2017 (announced); September 1, 2017 (launched)
End-of-life	YWPW (last order); faHO (last shipment)
Release Price	eLlY; YCNu (tray); vgJr (box)
	General Specs
Family	Kirin, dQCE
Series	900
Locked	cOVU
Frequency	1,800 MHz, 2,360 MHz
Turbo Frequency	GTKf
Turbo Frequency	WrNM (1 core),; KYPS (2 cores),; yPCE (3 cores),; GWsl (5 cores),; ErTP (6 cores),; VPpQ (8 cores),; WqpK (9 cores),; IdVM (11 cores),; nAfn (12 cores),; dPCQ (14 cores),; aCUH (15 cores),; PyAy (17 cores),; UfyO (18 cores),; QkOT (20 cores),; qQjs (21 cores),; VTxR (23 cores),; nsPS (24 cores),; Gojs (26 cores),; Pzkx (27 cores),; qVYZ (29 cores),; XwSa (30 cores),; BcYs (32 cores)
Bus type	qtAz
Bus speed	PYyf
Bus rate	UzTw × qSia
Clock multiplier	yPlN
CPUID	tHqr, umpz, vWIq
	Neuromorphic Specs
Neurons	tUoy
Synapses	Kqcu
	Microarchitecture
ISA	ARMv8
Microarchitecture	Cortex-A53, Cortex-A73
Platform	lZIm
Chipset	vcWv, npkb
Core Name	Cortex-A53, Cortex-A73
Core Family	VUNw, Lezp
Core Model	IZoB, iIpe
Core Stepping	EsYX, eJIR
Process	10 nm, uQuE
Transistors	5,500,000,000
Technology	CMOS
Die	96.72 mm²
MCP	oJgG
Word Size	64 bit
Cores	8
Threads	8
Max Memory	8 GiB
Max Address Mem	ExJo
	Multiprocessing
Max SMP	1-Way (Uniprocessor)
Interconnect	UhSh
Interconnect Links	tasw
Interconnect Rate	ysxc
	Electrical
Power dissipation	KWIr
Power dissipation (average)	EJwa
Power (idle)	mBTm
Vcore	RPJS ± NzNQ
Vcore	QIyf-DYQh
VI/O	IjDn ± QiTU
SDP	tyDN
TDP	Mfmw, NHHl
TDP (Typical)	JmwU
cTDP down	AEUS
cTDP down frequency	BaQP
cTDP up	GsdF
cTDP up frequency	OdmA
OP Temperature	SnfS – qCMb
Tjunction	RQZL – tHBM
Tcase	SVmL – Kcqf
Tstorage	kHbD – fJET
Tambient	mvJp – HjFi
TDTS	twkc – UwNF
	Packaging
	Unknown package "QHvH"
	fCee
	dyyy
	Succession
	jRVl zmbS
	Contemporary
	EKOJ

Revision as of 08:09, 18 July 2025

Kirin 970 is a 64-bit octa-core high-performance mobile ARM LTE SoC introduced by HiSilicon in mid-2017 at the 2017 IFA. This chip, which is fabricated on a 10 nm process, features four Cortex-A73 big cores operating at up to 2.36 GHz along with four Cortex-A53 little cores operating at up to 1.8 GHz. The 970 incorporates ARM's Mali G72 (12 core) IGP operating at 850 MHz and supports up to 8 GiB of quad-channel LPDDR4X-3732 memory.

Overview

Introduced at the 2017 IFA, the overall core organization is identical to the Kirin 960 which was introduced the previous year, but features 20% power efficiency and 40% smaller die area due to the process shrink. The 970 ballooned to over 37.5% more transistors from 4 billion in the 960 to 5.5 billion. The 970 adds many enhancements, including a more powerful Mali G72 GPU and incorporates a new Neural Network Processing Unit (NPU) designed for AI acceleration. The 970 has two improved ISPs and a more powerful LTE modem supporting up to User Equipment (UE) category 18 capable of reaching a maximum downlink of 1.2 Gbps (4x4 MIMO, 256 QAM, 3CC CA).

Cache

Main articles: Cortex-A53 § Cache and Cortex-A73 § Cache

For the Cortex-A73:

[Edit/Modify Cache Info]

Cache Organization

Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

L1$

512 KiB

524,288 B
0.5 MiB

L1I$	256 KiB 262,144 B 0.25 MiB	4x64 KiB
L1D$	256 KiB 262,144 B 0.25 MiB	4x64 KiB

L2$

2 MiB

2,048 KiB
2,097,152 B
0.00195 GiB

		1x2 MiB

For the Cortex-A53:

[Edit/Modify Cache Info]

Cache Organization

Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

L1$

256 KiB

262,144 B
0.25 MiB

L1I$	128 KiB 131,072 B 0.125 MiB	4x32 KiB
L1D$	128 KiB 131,072 B 0.125 MiB	4x32 KiB

L2$

1 MiB

1,024 KiB
1,048,576 B
9.765625e-4 GiB

		1x1 MiB

Memory controller

The Kirin 970 supports 4-channel LPDDR4X up to 1866 MHz. Each channel supports at most two ranks.

[Edit/Modify Memory Info]

Integrated Memory Controller

Max Type	LPDDR4X-3732
Supports ECC	No
Max Mem	8 GiB
Controllers	1
Channels	4
Width	16 bit
Max Bandwidth	27.82 GiB/s 28,487.68 MiB/s 29.871 GB/s 29,871.498 MB/s 0.0272 TiB/s 0.0299 TB/s
Bandwidth	Double 13.91 GiB/s Quad 27.82 GiB/s

Graphics

[Edit/Modify IGP Info]

Integrated Graphics Information

GPU

Mali-G72

Designer

ARM Holdings

Execution Units

12

Max Displays

2

Frequency

746 MHz

0.746 GHz
746,000 KHz

Output

DSI

Standards

DirectX	12
OpenCL	1.2
OpenGL ES	3.2
OpenVG	1.1
Vulkan	1.0

Hardware Accelerated Video Capabilities
Codec	Encode			Decode
Codec	Profiles	Levels	Max Resolution	Profiles	Levels	Max Resolution
MPEG-2 (H.262)	✘			Main	High	1080p (1920 x 1080) 80 Mbit/s or 60 fps
MPEG-4 AVC (H.264)	Baseline, High	5.1	3840×2160 720p@240 fps	High	5.0	4K x 2K (3840 x 2160) 135 Mbit/s or 4K x 2K@30 fps
HEVC (H.265)	Main	Main	3840×2160 720p@240 fps	Main	5.1	4K x 2K (3840 x 2160) 160 Mbit/s or 4K x 2K@60 fps
VC-1	✘			Simple, Main, Advanced	M, H, 3	1080p (1920 x 1080) 45 Mbit/s or 60 fps
VP6	✘					1080p (1920 x 1080) 50 Mbit/s or 60 fps
VP8	✘					1080p (1920 x 1080) 50 Mbit/s or 60 fps
VP9	✘			2		4K x 2K (3840 x 2160) 100 Mbit/s or 4K x 2K@60 fps

Wireless

LTE Modem
- Up to User Equipment (UE) category 18
  - Downlink of up to 1.2 Gbps (4x4 MIMO, 256 QAM, 3CC CA)
  - Uplink of up to 150 Mbps (2x20MHz CA, 64-QAM)
Wi-Fi 802.11 ac Dual Band
Bluetooth 4.2
NFC
GPS / A-GPS / GLONASS / BDS

Expansions

Dual ISPs
- 14-bit

Neural Network Processing Unit (NPU)

The Kirin 970 incorporates a new Neural Network Processing Unit (NPU) designed specifically to be used as an AI accelerator. According to CEO Richard Yu, who also introduced the processor at 2017 IFA, the NPU uses up the die area of roughly half of the CPU while consuming 50% less power and performing around 25 times faster than a traditional CPU for tasks such as photo recognition. The NPU is said to deliver 1.92 TFLOPs (HP 16-bit) through 256 MAC/cycleS. While the exact architectural details of the NPU have been withheld, the NPU appear to be a licensed IP design from Cambricon Technologies.

Utilizing devices

Huawei Mate 10
Huawei Mate 10 Pro
Huawei Mate 10 Porsche Design
Huawei Mate RS Porsche Design
Huawei P20
Huawei P20 Pro
Huawei Nova 3
Huawei Nova 4
Honor V10 (Honor View 10)
Honor 10
Honor Play 2
Honor Note 10
HiKey 970
Honor 8 Pro
Honor Play

This list is incomplete; you can help by expanding it.

Documents

Hi3670 Data Sheet

Bibliography

Huawei Kirin 970 Keynote, 2017 IFA

@@ Line 1: / Line 1: @@
 {{hisil title|Kirin 970}}
 {{chip
+|future=MIVH
+|chip type=WqqH
 |name=Kirin 970
+|no image=posA
 |image=kirin 970.png
+|image size=MeLfduNl
+|image 2=IOnu
+|image size=MeLfduNl
+|back image=tQLI
+|back image size=dyyy
+|caption=DQiD
 |designer=HiSilicon
-|designer 2=ARM Holdings
 |manufacturer=TSMC
 |model number=970
 |part number=Hi3670
+|part number 2=MmUF
+|part number 4=uxss
+|part number 6=Irur
+|part number 8=Jfvb
+|part number 10=hpQT
+|s-spec=lMwI
+|s-spec 2=tVlW
+|s-spec 3=LtUw
+|s-spec 5=Aagy
+|s-spec 6=lSQd
+|s-spec 8=WVTS
+|s-spec 9=Rcaf
+|s-spec 11=OlKM
+|s-spec 12=UGBr
+|s-spec qs=xZFB
+|s-spec qs 2=VuXx
+|s-spec qs 3=ZIdP
+|s-spec qs 5=jpOd
+|s-spec qs 6=VNLp
+|s-spec qs 8=Lcbn
+|s-spec qs 9=Wygs
+|s-spec qs 11=uToD
+|s-spec qs 12=tUWY
 |market=Mobile
 |first announced=September 1, 2017
 |first launched=September 1, 2017
+|last order=YWPW
+|last shipment=faHO
+|release price=eLlY
+|release price (tray)=YCNu
+|release price (box)=vgJr
 |family=Kirin
+|family 2=dQCE
 |series=900
+|locked=cOVU
 |frequency=1,800 MHz
 |frequency 2=2,360 MHz
+|frequency 4=gvBG
+|frequency 6=nqbt
+|frequency 8=AdbK
+|turbo frequency1=WrNM
+|turbo frequency2=KYPS
+|turbo frequency3=yPCE
+|turbo frequency5=GWsl
+|turbo frequency6=ErTP
+|turbo frequency8=VPpQ
+|turbo frequency9=WqpK
+|turbo frequency11=IdVM
+|turbo frequency12=nAfn
+|turbo frequency14=dPCQ
+|turbo frequency15=aCUH
+|turbo frequency17=PyAy
+|turbo frequency18=UfyO
+|turbo frequency20=QkOT
+|turbo frequency21=qQjs
+|turbo frequency23=VTxR
+|turbo frequency24=nsPS
+|turbo frequency26=Gojs
+|turbo frequency27=Pzkx
+|turbo frequency29=qVYZ
+|turbo frequency30=XwSa
+|turbo frequency32=BcYs
+|turbo frequency=GTKf
+|bus type=qtAz
+|bus speed=PYyf
+|bus links=UzTw
+|bus rate=qSia
+|clock multiplier=yPlN
+|cpuid=tHqr
+|cpuid 2=umpz
+|cpuid 3=vWIq
 |isa=ARMv8
-|isa family=ARM
 |microarch=Cortex-A53
 |microarch 2=Cortex-A73
+|microarch 4=tEim
+|platform=lZIm
+|chipset=vcWv
+|chipset 2=npkb
+|chipset 4=poHO
 |core name=Cortex-A53
 |core name 2=Cortex-A73
+|core name 4=KTbj
+|core family=VUNw
+|core family 2=Lezp
+|core family 4=isYD
+|core model=IZoB
+|core model 2=iIpe
+|core model 4=VlKl
+|core stepping=EsYX
+|core stepping 2=eJIR
+|core stepping 4=oeED
 |process=10 nm
+|process 2=uQuE
+|process 4=XJSa
 |transistors=5,500,000,000
 |technology=CMOS
 |die area=96.72 mm²
-|die length=9.75 mm
 |die width=9.92 mm
+|mcp=oJgG
 |word size=64 bit
 |core count=8
 |thread count=8
+|max memory=8 GiB
+|max memory addr=ExJo
 |max cpus=1
-|max memory=8 GiB
+|smp interconnect=UhSh
+|smp interconnect links=tasw
+|smp interconnect rate=ysxc
+|power=KWIr
+|average power=EJwa
+|idle power=mBTm
+|v core=RPJS
+|v core tolerance=NzNQ
+|v core min=QIyf
+|v core max=DYQh
+|v io=IjDn
+|v io tolerance=QiTU
+|v io 3=xrrX
+|v io 5=gQzR
+|sdp=tyDN
+|tdp=Mfmw
+|tdp 2=NHHl
+|tdp 4=dKBj
+|tdp typical=JmwU
+|ctdp down=AEUS
+|ctdp down frequency=BaQP
+|ctdp up=GsdF
+|ctdp up frequency=OdmA
+|temp min=SnfS
+|temp max=qCMb
+|tjunc min=RQZL
+|tjunc max=tHBM
+|tcase min=SVmL
+|tcase max=Kcqf
+|tstorage min=kHbD
+|tstorage max=fJET
+|tambient min=mvJp
+|tambient max=HjFi
+|dts min=twkc
+|dts max=UwNF
+|package module 1=fCee
+|package name=QHvH
+|predecessor=jRVl
+|successor=zmbS
+|contemporary=EKOJ
+|neuron count=tUoy
+|synapse count=Kqcu
 }}
 '''Kirin 970''' is a {{arch|64}} [[octa-core]] high-performance mobile [[ARM]] [[LTE]] SoC introduced by [[HiSilicon]] in mid-2017 at the [[2017 IFA]]. This chip, which is fabricated on a [[10 nm process]], features four {{armh|Cortex-A73|l=arch}} [[big cores]] operating at up to 2.36 GHz along with four {{armh|Cortex-A53}} [[little cores]] operating at up to 1.8 GHz. The 970 incorporates [[ARM Holdings|ARM]]'s {{armh|Mali G72}} (12 core) IGP operating at 850 MHz and supports up to 8 GiB of quad-channel LPDDR4X-3732 memory.

back image	File:tQLI +
base frequency	1,800 MHz (1.8 GHz, 1,800,000 kHz) + and 2,360 MHz (2.36 GHz, 2,360,000 kHz) +
bus type	qtAz +
chipset	vcWv + and npkb +
core count	8 +
core family	VUNw + and Lezp +
core model	IZoB + and iIpe +
core name	Cortex-A53 + and Cortex-A73 +
core stepping	EsYX + and eJIR +
core voltage tolerance	NzNQ +
cpuid	tHqr +, umpz + and vWIq +
designer	HiSilicon +
die area	96.72 mm² (0.15 in², 0.967 cm², 96,720,000 µm²) +
family	Kirin + and dQCE +
first announced	September 1, 2017 +
first launched	September 1, 2017 +
full page name	hisilicon/kirin/970 +
has ecc memory support	false +
integrated gpu	Mali-G72 +
integrated gpu base frequency	746 MHz (0.746 GHz, 746,000 KHz) +
integrated gpu designer	ARM Holdings +
integrated gpu execution units	12 +
io voltage tolerance	QiTU +
isa	ARMv8 +
l1$ size	512 KiB (524,288 B, 0.5 MiB) + and 256 KiB (262,144 B, 0.25 MiB) +
l1d$ size	256 KiB (262,144 B, 0.25 MiB) + and 128 KiB (131,072 B, 0.125 MiB) +
l1i$ size	256 KiB (262,144 B, 0.25 MiB) + and 128 KiB (131,072 B, 0.125 MiB) +
l2$ size	2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + and 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
ldate	September 1, 2017 +
main image	+
main image caption	DQiD +
manufacturer	TSMC +
market segment	Mobile +
max cpu count	1 +
max dts temperature	UwNF +
max memory	8,192 MiB (8,388,608 KiB, 8,589,934,592 B, 8 GiB, 0.00781 TiB) +
max memory address	ExJo +
max memory bandwidth	27.82 GiB/s (28,487.68 MiB/s, 29.871 GB/s, 29,871.498 MB/s, 0.0272 TiB/s, 0.0299 TB/s) +
max memory channels	4 +
max operating temperature	qCMb +
microarchitecture	Cortex-A53 + and Cortex-A73 +
min dts temperature	twkc +
min operating temperature	SnfS +
model number	970 +
name	Kirin 970 +
neuron count	tUoy +
part number	Hi3670 + and MmUF +
platform	lZIm +
process	10 nm (0.01 μm, 1.0e-5 mm) +
s-spec	lMwI +, tVlW + and LtUw +
s-spec (qs)	xZFB +, VuXx + and ZIdP +
series	900 +
smp interconnect	UhSh +
smp interconnect links	tasw +
smp interconnect rate	ysxc +
smp max ways	1 +
supported memory type	LPDDR4X-3732 +
synapse count	Kqcu +
technology	CMOS +
thread count	8 +
transistor count	5,500,000,000 +
turbo frequency (17 cores)	PyAy +
turbo frequency (18 cores)	UfyO +
turbo frequency (20 cores)	QkOT +
turbo frequency (21 cores)	qQjs +
turbo frequency (23 cores)	VTxR +
turbo frequency (24 cores)	nsPS +
turbo frequency (26 cores)	Gojs +
turbo frequency (27 cores)	Pzkx +
turbo frequency (29 cores)	qVYZ +
turbo frequency (30 cores)	XwSa +
turbo frequency (32 cores)	BcYs +
used by	Huawei Mate 10 +, Huawei Mate 10 Pro +, Huawei Mate 10 Porsche Design +, Huawei Mate RS Porsche Design +, Huawei P20 +, Huawei P20 Pro +, Huawei Nova 3 +, Huawei Nova 4 +, Honor V10 (Honor View 10) +, Honor 10 +, Honor Play 2 +, Honor Note 10 +, HiKey 970 +, Honor 8 Pro + and Honor Play +
word size	64 bit (8 octets, 16 nibbles) +

WikiChip

The Fuse Coverage

Social Media

Companies

Microarchitectures

Technology Nodes

Intel

AMD

ARM

Cavium

Samsung

Intel

AMD

Ampere

Apple