Semiconductor & Computer Engineering
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Difference between revisions of "Template:x86 features"
(linked to AMD's SME/TSME/SEV) |
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-->{{#if: {{istrue|{{{sse42|}}}}} | <tr><th style="width: 100px;">SSE4.2</th><td>{{x86|SSE4.2|Streaming SIMD Extensions 4.2}}</td></tr> }}<!-- | -->{{#if: {{istrue|{{{sse42|}}}}} | <tr><th style="width: 100px;">SSE4.2</th><td>{{x86|SSE4.2|Streaming SIMD Extensions 4.2}}</td></tr> }}<!-- | ||
-->{{#if: {{istrue|{{{sse4a|}}}}} | <tr><th style="width: 100px;">SSE4a</th><td>{{x86|SSE4a|Streaming SIMD Extensions 4a}}</td></tr> }}<!-- | -->{{#if: {{istrue|{{{sse4a|}}}}} | <tr><th style="width: 100px;">SSE4a</th><td>{{x86|SSE4a|Streaming SIMD Extensions 4a}}</td></tr> }}<!-- | ||
| + | -->{{#if: {{istrue|{{{sse_gfni|}}}}} | <tr><th style="width: 100px;">GFNI</th><td>{{x86|GFNI|SSE Galois Field New Instructions}}</td></tr> }}<!-- | ||
-->{{#if: {{istrue|{{{avx|}}}}} | <tr><th style="width: 100px;">AVX</th><td>{{x86|AVX|Advanced Vector Extensions}}</td></tr>[[has feature::Advanced Vector Extensions| ]][[has advanced vector extensions::true| ]] }}<!-- | -->{{#if: {{istrue|{{{avx|}}}}} | <tr><th style="width: 100px;">AVX</th><td>{{x86|AVX|Advanced Vector Extensions}}</td></tr>[[has feature::Advanced Vector Extensions| ]][[has advanced vector extensions::true| ]] }}<!-- | ||
| + | -->{{#if: {{istrue|{{{avx_gfni|}}}}} | <tr><th style="width: 100px;">AVX+GFNI</th><td>{{x86|GFNI|AVX Galois Field New Instructions}}</td></tr> }}<!-- | ||
-->{{#if: {{istrue|{{{avx2|}}}}} | <tr><th style="width: 100px;">AVX2</th><td>{{x86|AVX2|Advanced Vector Extensions 2}}</td></tr>[[has feature::Advanced Vector Extensions 2| ]][[has advanced vector extensions 2::true| ]] }}<!-- | -->{{#if: {{istrue|{{{avx2|}}}}} | <tr><th style="width: 100px;">AVX2</th><td>{{x86|AVX2|Advanced Vector Extensions 2}}</td></tr>[[has feature::Advanced Vector Extensions 2| ]][[has advanced vector extensions 2::true| ]] }}<!-- | ||
| − | -->{{#if: {{istrue|{{{avx512f|{{{avx512cd|{{{avx512er|{{{avx512pf|{{{avx512bw|{{{avx512dq|{{{avx512vl|{{{avx512ifma|{{{avx512vbmi|{{{avx5124fmaps|{{{avx5124vnniw|{{{avx512vpopcntdq|}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}} | <tr><th style="width: 100px;">AVX-512</th><td>{{x86|avx-512|Advanced Vector 512-bit}} {{#if: {{{avx512units|}}}|([[number of avx-512 execution units::{{{avx512units}}}]] Unit{{#ifexpr: {{{avx512units}}} > 1|s}})}}</td></tr> }}<!-- | + | -->{{#if: {{istrue|{{{avx512f|{{{avx512cd|{{{avx512er|{{{avx512pf|{{{avx512bw|{{{avx512dq|{{{avx512vl|{{{avx512ifma|{{{avx512vbmi|{{{avx5124fmaps|{{{avx5124vnniw|{{{avx512vpopcntdq|{{{avx512vnni|{{{avx512gfni|{{{avx512vaes|{{{avx512vbmi2|{{{avx512bitalg|{{{avx512vpclmulqdq|{{{sse_gfni|{{{avx_gfni}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}} | <tr><th style="width: 100px;">AVX-512</th><td>{{x86|avx-512|Advanced Vector 512-bit}} {{#if: {{{avx512units|}}}|([[number of avx-512 execution units::{{{avx512units}}}]] Unit{{#ifexpr: {{{avx512units}}} > 1|s}})}}</td></tr> }}<!-- |
| − | -->{{#if: {{istrue|{{{avx512f|}}}}} | <tr><th style="width: 100px;">AVX512F</th><td>AVX-512 Foundation</td></tr> }}<!-- | + | -->{{#if: {{istrue|{{{avx512f|}}}}} | <tr><th style="width: 100px;">AVX512F</th><td>AVX-512 Foundation</td></tr>[[has feature::Advanced Vector Extensions 512| ]][[has advanced vector extensions 512::true| ]]}}<!-- |
-->{{#if: {{istrue|{{{avx512cd|}}}}} | <tr><th style="width: 100px;">AVX512CD</th><td>AVX-512 Conflict Detection</td></tr> }}<!-- | -->{{#if: {{istrue|{{{avx512cd|}}}}} | <tr><th style="width: 100px;">AVX512CD</th><td>AVX-512 Conflict Detection</td></tr> }}<!-- | ||
-->{{#if: {{istrue|{{{avx512er|}}}}} | <tr><th style="width: 100px;">AVX512ER</th><td>AVX-512 Exponential and Reciprocal</td></tr> }}<!-- | -->{{#if: {{istrue|{{{avx512er|}}}}} | <tr><th style="width: 100px;">AVX512ER</th><td>AVX-512 Exponential and Reciprocal</td></tr> }}<!-- | ||
-->{{#if: {{istrue|{{{avx512pf|}}}}} | <tr><th style="width: 100px;">AVX512PF</th><td>AVX-512 Prefetch</td></tr> }}<!-- | -->{{#if: {{istrue|{{{avx512pf|}}}}} | <tr><th style="width: 100px;">AVX512PF</th><td>AVX-512 Prefetch</td></tr> }}<!-- | ||
-->{{#if: {{istrue|{{{avx512bw|}}}}} | <tr><th style="width: 100px;">AVX512BW</th><td>AVX-512 Byte and Word</td></tr> }}<!-- | -->{{#if: {{istrue|{{{avx512bw|}}}}} | <tr><th style="width: 100px;">AVX512BW</th><td>AVX-512 Byte and Word</td></tr> }}<!-- | ||
| − | -->{{#if: {{istrue|{{{avx512dq|}}}}} | <tr><th style="width: 100px;">AVX512DQ</th><td>AVX-512 | + | -->{{#if: {{istrue|{{{avx512dq|}}}}} | <tr><th style="width: 100px;">AVX512DQ</th><td>{{x86|AVX512DQ|AVX-512 Doubleword and Quadword Instructions}}</td></tr> }}<!-- |
-->{{#if: {{istrue|{{{avx512vl|}}}}} | <tr><th style="width: 100px;">AVX512VL</th><td>AVX-512 Vector Length</td></tr> }}<!-- | -->{{#if: {{istrue|{{{avx512vl|}}}}} | <tr><th style="width: 100px;">AVX512VL</th><td>AVX-512 Vector Length</td></tr> }}<!-- | ||
| − | -->{{#if: {{istrue|{{{avx512ifma|}}}}} | <tr><th style="width: 100px;"> | + | -->{{#if: {{istrue|{{{avx512ifma|}}}}} | <tr><th style="width: 100px;">AVX512_IFMA</th><td>{{x86|AVX512_IFMA|AVX-512 Integer Fused Multiply-Add}}</td></tr> }}<!-- |
| − | -->{{#if: {{istrue|{{{avx512vbmi|}}}}} | <tr><th style="width: 100px;"> | + | -->{{#if: {{istrue|{{{avx512vbmi|}}}}} | <tr><th style="width: 100px;">AVX512_VBMI</th><td>{{x86|AVX512_VBMI|AVX-512 Vector Bit Manipulation Instructions}}</td></tr> }}<!-- |
| − | -->{{#if: {{istrue|{{{avx5124fmaps|}}}}} | <tr><th style="width: 100px;"> | + | -->{{#if: {{istrue|{{{avx5124fmaps|}}}}} | <tr><th style="width: 100px;">AVX512_4FMAPS</th><td>{{x86|AVX512_4FMAPS|AVX-512 Fused Multiply-Accumulate Packed Single Precision}}</td></tr> }}<!-- |
| − | -->{{#if: {{istrue|{{{avx5124vnniw|}}}}} | <tr><th style="width: 100px;"> | + | -->{{#if: {{istrue|{{{avx512vnni|}}}}} | <tr><th style="width: 100px;">AVX512_VNNI</th><td>{{x86|AVX512_VNNI|AVX-512 Vector Neural Network Instructions}}</td></tr> }}<!-- |
| − | -->{{#if: {{istrue|{{{avx512vpopcntdq|}}}}} | <tr><th style="width: 100px;"> | + | -->{{#if: {{istrue|{{{avx5124vnniw|}}}}} | <tr><th style="width: 100px;">AVX512_4VNNIW</th><td>{{x86|AVX512_4VNNIW|AVX-512 Vector Neural Network Instructions Word Variable Precision}}</td></tr> }}<!-- |
| + | -->{{#if: {{istrue|{{{avx512vpopcntdq|}}}}} | <tr><th style="width: 100px;">AVX512_VPOPCNTDQ</th><td>{{x86|AVX512_VPOPCNTDQ|AVX-512 Vector Population Count Doubleword and Quadword}}</td></tr> }}<!-- | ||
| + | -->{{#if: {{istrue|{{{avx512gfni|}}}}} | <tr><th style="width: 100px;">AVX512F+GFNI</th><td>{{x86|GFNI|AVX-512 Galois Field New Instructions}}</td></tr> }}<!-- | ||
| + | -->{{#if: {{istrue|{{{avx512vaes|}}}}} | <tr><th style="width: 100px;">AVX512F+VAES</th><td>{{x86|VAES|AVX-512 Vector AES Instructions}}</td></tr> }}<!-- | ||
| + | -->{{#if: {{istrue|{{{avx512vbmi2|}}}}} | <tr><th style="width: 100px;">AVX512_VBMI2</th><td>{{x86|AVX512_VBMI2|AVX-512 Vector Bit Manipulation Instructions 2}}</td></tr> }}<!-- | ||
| + | -->{{#if: {{istrue|{{{avx512bitalg|}}}}} | <tr><th style="width: 100px;">AVX512_BITALG</th><td>{{x86|AVX512_BITALG|AVX-512 Bit Algorithms}}</td></tr> }}<!-- | ||
| + | -->{{#if: {{istrue|{{{avx512vpclmulqdq|}}}}} | <tr><th style="width: 100px;">AVX512F+VPCLMULQDQ</th><td>{{x86|VPCLMULQDQ|Vector Carry-Less Multiplication of Quadwords}}</td></tr> }}<!-- | ||
| + | -->{{#if: {{istrue|{{{bfloat16|}}}}} | <tr><th style="width: 100px;">AVX512_BF16</th><td>{{x86|AVX512_BF16|AVX-512 BFloat16 Instructions}}</td></tr>}}<!-- | ||
-->{{#if: {{istrue|{{{abm|}}}}} | <tr><th style="width: 100px;">ABM</th><td>{{x86|ABM|Advanced Bit Manipulation}}</td></tr> }}<!-- | -->{{#if: {{istrue|{{{abm|}}}}} | <tr><th style="width: 100px;">ABM</th><td>{{x86|ABM|Advanced Bit Manipulation}}</td></tr> }}<!-- | ||
-->{{#if: {{istrue|{{{tbm|}}}}} | <tr><th style="width: 100px;">TBM</th><td>{{x86|TBM|Trailing Bit Manipulation}}</td></tr> }}<!-- | -->{{#if: {{istrue|{{{tbm|}}}}} | <tr><th style="width: 100px;">TBM</th><td>{{x86|TBM|Trailing Bit Manipulation}}</td></tr> }}<!-- | ||
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-->{{#if: {{istrue|{{{tbt1|}}}}} | <tr><th style="width: 100px;">TBT 1.0</th><td>{{intel|Turbo Boost Technology}} 1.0 [[has feature::Turbo Boost Technology 1.0| ]][[has intel turbo boost technology 1_0::true| ]]</td></tr> }}<!-- | -->{{#if: {{istrue|{{{tbt1|}}}}} | <tr><th style="width: 100px;">TBT 1.0</th><td>{{intel|Turbo Boost Technology}} 1.0 [[has feature::Turbo Boost Technology 1.0| ]][[has intel turbo boost technology 1_0::true| ]]</td></tr> }}<!-- | ||
-->{{#if: {{istrue|{{{tbt2|}}}}} | <tr><th style="width: 100px;">TBT 2.0</th><td>{{intel|Turbo Boost Technology}} 2.0[[has feature::Turbo Boost Technology 2.0| ]][[has intel turbo boost technology 2_0::true| ]]</td></tr> }}<!-- | -->{{#if: {{istrue|{{{tbt2|}}}}} | <tr><th style="width: 100px;">TBT 2.0</th><td>{{intel|Turbo Boost Technology}} 2.0[[has feature::Turbo Boost Technology 2.0| ]][[has intel turbo boost technology 2_0::true| ]]</td></tr> }}<!-- | ||
| − | -->{{#if: {{istrue|{{{tbmt3|}}}}} | <tr><th style="width: 100px;">TBMT 3.0</th><td>Turbo Boost Max Technology 3.0[[has feature::Turbo Boost Max Technology 3.0| ]][[has intel turbo boost max technology 3_0::true| ]]</td></tr> }}<!-- | + | -->{{#if: {{istrue|{{{tbmt3|}}}}} | <tr><th style="width: 100px;">TBMT 3.0</th><td>{{intel|Turbo Boost Max Technology}} 3.0[[has feature::Turbo Boost Max Technology 3.0| ]][[has intel turbo boost max technology 3_0::true| ]]</td></tr> }}<!-- |
| + | -->{{#if: {{istrue|{{{tvb|}}}}} | <tr><th style="width: 100px;">TVB</th><td>{{intel|Thermal Velocity Boost}} [[has feature::Thermal Velocity Boost| ]][[has intel thermal velocity boost::true| ]]</td></tr> }}<!-- | ||
-->{{#if: {{istrue|{{{bpt|}}}}} | <tr><th style="width: 100px;">BPT</th><td>Burst Performance Technology[[has feature::Burst Performance Technology| ]][[has intel burst performance technology::true| ]]</td></tr> }}<!-- | -->{{#if: {{istrue|{{{bpt|}}}}} | <tr><th style="width: 100px;">BPT</th><td>Burst Performance Technology[[has feature::Burst Performance Technology| ]][[has intel burst performance technology::true| ]]</td></tr> }}<!-- | ||
-->{{#if: {{istrue|{{{eist|}}}}} | <tr><th style="width: 100px;">EIST</th><td>{{intel|Enhanced SpeedStep Technology}}[[has intel enhanced speedstep technology::true| ]][[has feature::Enhanced SpeedStep Technology| ]]</td></tr> }}<!-- | -->{{#if: {{istrue|{{{eist|}}}}} | <tr><th style="width: 100px;">EIST</th><td>{{intel|Enhanced SpeedStep Technology}}[[has intel enhanced speedstep technology::true| ]][[has feature::Enhanced SpeedStep Technology| ]]</td></tr> }}<!-- | ||
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-->{{#if: {{istrue|{{{amdtsme|}}}}} | <tr><th style="width: 100px;">TSME</th><td>[[x86/sme#Transparent_SME|Transparent SME]]</td></tr>[[has amd transparent secure memory encryption technology::true| ]] }}<!-- | -->{{#if: {{istrue|{{{amdtsme|}}}}} | <tr><th style="width: 100px;">TSME</th><td>[[x86/sme#Transparent_SME|Transparent SME]]</td></tr>[[has amd transparent secure memory encryption technology::true| ]] }}<!-- | ||
-->{{#if: {{istrue|{{{amdsev|}}}}} | <tr><th style="width: 100px;">SEV</th><td>[[x86/sme#Secure_Encrypted_Virtualization|Secure Encrypted Virtualization]]</td></tr>[[has amd secure encrypted virtualization technology::true| ]] }}<!-- | -->{{#if: {{istrue|{{{amdsev|}}}}} | <tr><th style="width: 100px;">SEV</th><td>[[x86/sme#Secure_Encrypted_Virtualization|Secure Encrypted Virtualization]]</td></tr>[[has amd secure encrypted virtualization technology::true| ]] }}<!-- | ||
| − | -->{{#if: {{istrue|{{{ept|}}}}} | <tr><th style="width: 100px;">EPT</th><td>[[has extended page tables support::true| ]]Extended Page Tables ([[has second level address translation support::true| ]][[Second Level Address Translation|SLAT]])</td></tr> }}<!-- | + | -->{{#if: {{istrue|{{{ept|}}}}} | <tr><th style="width: 100px;">EPT</th><td>[[has feature::Extended Page Tables| ]][[has extended page tables support::true| ]]Extended Page Tables ([[has second level address translation support::true| ]][[Second Level Address Translation|SLAT]])</td></tr> }}<!-- |
-->{{#if: {{istrue|{{{rvi|}}}}} | <tr><th style="width: 100px;">RVI</th><td>Rapid Virtualization Indexing ([[has second level address translation support::true| ]][[Second Level Address Translation|SLAT]])</td></tr> }}<!-- | -->{{#if: {{istrue|{{{rvi|}}}}} | <tr><th style="width: 100px;">RVI</th><td>Rapid Virtualization Indexing ([[has second level address translation support::true| ]][[Second Level Address Translation|SLAT]])</td></tr> }}<!-- | ||
-->{{#if: {{istrue|{{{tsx|}}}}} | <tr><th style="width: 100px;">TSX</th><td>Transactional Synchronization Extensions[[has feature::Transactional Synchronization Extensions| ]][[has transactional synchronization extensions::true| ]]</td></tr> }}<!-- | -->{{#if: {{istrue|{{{tsx|}}}}} | <tr><th style="width: 100px;">TSX</th><td>Transactional Synchronization Extensions[[has feature::Transactional Synchronization Extensions| ]][[has transactional synchronization extensions::true| ]]</td></tr> }}<!-- | ||
| − | -->{{#if: {{istrue|{{{mpx|}}}}} | <tr><th style="width: 100px;">MPX</th><td>Memory Protection Extensions</td></tr> }}<!-- | + | -->{{#if: {{istrue|{{{mpx|}}}}} | <tr><th style="width: 100px;">MPX</th><td>[[x86/has memory protection extensions::true| ]][[has feature::Memory Protection Extensions| ]]Memory Protection Extensions</td></tr> }}<!-- |
| − | -->{{#if: {{istrue|{{{sgx|}}}}} | <tr><th style="width: 100px;">SGX</th><td>Software Guard Extensions</td></tr> }}<!-- | + | -->{{#if: {{istrue|{{{sgx|}}}}} | <tr><th style="width: 100px;">SGX</th><td>[[x86/has software guard extensions::true| ]][[has feature::Software Guard Extensions]]</td></tr> }}<!-- |
-->{{#if: {{istrue|{{{securekey|}}}}} | <tr><th style="width: 100px;">Secure Key</th><td>Secure Key Technology</td></tr>[[has feature::Secure Key Technology| ]][[has intel secure key technology::true| ]] }}<!-- | -->{{#if: {{istrue|{{{securekey|}}}}} | <tr><th style="width: 100px;">Secure Key</th><td>Secure Key Technology</td></tr>[[has feature::Secure Key Technology| ]][[has intel secure key technology::true| ]] }}<!-- | ||
-->{{#if: {{istrue|{{{osguard|}}}}} | <tr><th style="width: 100px;">SMEP</th><td>OS Guard Technology</td></tr>[[has feature::OS Guard| ]][[has intel supervisor mode execution protection::true| ]] }}<!-- | -->{{#if: {{istrue|{{{osguard|}}}}} | <tr><th style="width: 100px;">SMEP</th><td>OS Guard Technology</td></tr>[[has feature::OS Guard| ]][[has intel supervisor mode execution protection::true| ]] }}<!-- | ||
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-->{{#if: {{istrue|{{{mwt|}}}}} | <tr><th style="width: 100px;">MWT</th><td>My WiFi Technology</td></tr>[[has feature::My WiFi Technology| ]][[has intel my wifi technology support::true| ]] }}<!-- | -->{{#if: {{istrue|{{{mwt|}}}}} | <tr><th style="width: 100px;">MWT</th><td>My WiFi Technology</td></tr>[[has feature::My WiFi Technology| ]][[has intel my wifi technology support::true| ]] }}<!-- | ||
-->{{#if: {{istrue|{{{sipp|}}}}} | <tr><th style="width: 100px;">SIPP</th><td>Stable Image Platform Program</td></tr>[[has feature::Stable Image Platform Program| ]][[has intel stable image platform program support::true| ]] }}<!-- | -->{{#if: {{istrue|{{{sipp|}}}}} | <tr><th style="width: 100px;">SIPP</th><td>Stable Image Platform Program</td></tr>[[has feature::Stable Image Platform Program| ]][[has intel stable image platform program support::true| ]] }}<!-- | ||
| + | -->{{#if: {{istrue|{{{dlboost|}}}}} | <tr><th style="width: 100px;">DL Boost</th><td>{{intel|dl boost|Deep Learning Boost}}</td></tr>[[has feature::Deep Learning Boost| ]][[has intel deep learning boost::true| ]] }}<!-- | ||
-->{{#if: {{istrue|{{{att|}}}}} | <tr><th style="width: 100px;">ATT</th><td>Anti-Theft Technology</td></tr> }}<!-- | -->{{#if: {{istrue|{{{att|}}}}} | <tr><th style="width: 100px;">ATT</th><td>Anti-Theft Technology</td></tr> }}<!-- | ||
-->{{#if: {{istrue|{{{ipt|}}}}} | <tr><th style="width: 100px;">IPT</th><td>Identity Protection Technology</td></tr>[[has feature::Identity Protection Technology| ]][[has intel identity protection technology support::true| ]] }}<!-- | -->{{#if: {{istrue|{{{ipt|}}}}} | <tr><th style="width: 100px;">IPT</th><td>Identity Protection Technology</td></tr>[[has feature::Identity Protection Technology| ]][[has intel identity protection technology support::true| ]] }}<!-- | ||
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-->{{#if: {{istrue|{{{sensemi|}}}}} | <tr><th style="width: 100px;">SenseMI</th><td>SenseMI Technology</td></tr>[[has feature::SenseMI Technology| ]][[has amd sensemi technology::true| ]] }}<!-- | -->{{#if: {{istrue|{{{sensemi|}}}}} | <tr><th style="width: 100px;">SenseMI</th><td>SenseMI Technology</td></tr>[[has feature::SenseMI Technology| ]][[has amd sensemi technology::true| ]] }}<!-- | ||
-->{{#if: {{istrue|{{{xfr|}}}}} | <tr><th style="width: 100px;">XFR</th><td>{{amd|Extended Frequency Range}}</td></tr>[[has feature::Extended Frequency Range| ]][[has amd extended frequency range::true| ]] }}<!-- | -->{{#if: {{istrue|{{{xfr|}}}}} | <tr><th style="width: 100px;">XFR</th><td>{{amd|Extended Frequency Range}}</td></tr>[[has feature::Extended Frequency Range| ]][[has amd extended frequency range::true| ]] }}<!-- | ||
| + | -->{{#if: {{istrue|{{{xfr2|}}}}} | <tr><th style="width: 100px;">XFR 2</th><td>{{amd|Extended Frequency Range|Extended Frequency Range 2}}</td></tr>[[has feature::Extended Frequency Range 2| ]][[has amd extended frequency range 2::true| ]] }}<!-- | ||
-->{{#if: {{istrue|{{{mxfr|}}}}} | <tr><th style="width: 100px;">mXFR</th><td>{{amd|Mobile XFR}}</td></tr>[[has feature::Mobile Extended Frequency Range| ]][[has amd mobile extended frequency range::true| ]] }}<!-- | -->{{#if: {{istrue|{{{mxfr|}}}}} | <tr><th style="width: 100px;">mXFR</th><td>{{amd|Mobile XFR}}</td></tr>[[has feature::Mobile Extended Frequency Range| ]][[has amd mobile extended frequency range::true| ]] }}<!-- | ||
-->{{#if: {{istrue|{{{amdpb|}}}}} | <tr><th style="width: 100px;">Boost</th><td>{{amd|Precision Boost}}</td></tr>[[has feature::Precision Boost| ]][[has amd precision boost::true| ]] }}<!-- | -->{{#if: {{istrue|{{{amdpb|}}}}} | <tr><th style="width: 100px;">Boost</th><td>{{amd|Precision Boost}}</td></tr>[[has feature::Precision Boost| ]][[has amd precision boost::true| ]] }}<!-- | ||
-->{{#if: {{istrue|{{{amdpb2|}}}}} | <tr><th style="width: 100px;">Boost 2</th><td>{{amd|Precision Boost 2}}</td></tr>[[has feature::Precision Boost 2| ]][[has amd precision boost 2::true| ]] }}<!-- | -->{{#if: {{istrue|{{{amdpb2|}}}}} | <tr><th style="width: 100px;">Boost 2</th><td>{{amd|Precision Boost 2}}</td></tr>[[has feature::Precision Boost 2| ]][[has amd precision boost 2::true| ]] }}<!-- | ||
| + | -->{{#if: {{istrue|{{{amdpbod|}}}}} | <tr><th style="width: 100px;">PBO</th><td>{{amd|Precision Boost Overdrive}}</td></tr>[[has feature::Precision Boost Overdrive| ]][[has amd precision boost overdrive::true| ]] }}<!-- | ||
-->{{#if: {{istrue|{{{intqat|}}}}} | <tr><th style="width: 100px;">QAT</th><td>Integrated {{intel|QuickAssist Technology}}</td></tr>[[has feature::Integrated QuickAssist Technology| ]][[has integrated intel quickassist technology::true| ]] }}<!-- | -->{{#if: {{istrue|{{{intqat|}}}}} | <tr><th style="width: 100px;">QAT</th><td>Integrated {{intel|QuickAssist Technology}}</td></tr>[[has feature::Integrated QuickAssist Technology| ]][[has integrated intel quickassist technology::true| ]] }}<!-- | ||
| + | -->{{#if: {{istrue|{{{tme|}}}}} | <tr><th style="width: 100px;">TME</th><td>{{x86|Total Memory Encryption}}</td></tr>[[has feature::Total Memory Encryption| ]][[has total memory encryption::true| ]] }}<!-- | ||
| + | -->{{#if: {{istrue|{{{mktme|}}}}} | <tr><th style="width: 100px;">MKTME</th><td>{{x86|Multi-Key Total Memory Encryption}}</td></tr>[[has feature::Multi-Key Total Memory Encryption| ]][[has multi-key total memory encryption::true| ]] }}<!-- | ||
--></table> | --></table> | ||
</td> | </td> | ||
Latest revision as of 16:18, 15 March 2023
[Edit/Modify Supported Features]
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Supported x86 Extensions & Processor Features
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