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Difference between revisions of "intel/xeon silver/4116t"
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{{intel title|Xeon Silver 4116T}} | {{intel title|Xeon Silver 4116T}} | ||
− | {{ | + | {{chip |
|name=Xeon Silver 4116T | |name=Xeon Silver 4116T | ||
|image=skylake sp (basic).png | |image=skylake sp (basic).png | ||
Line 6: | Line 6: | ||
|manufacturer=Intel | |manufacturer=Intel | ||
|model number=4116T | |model number=4116T | ||
− | |part number= | + | |part number=CD8067303645400 |
+ | |s-spec=SR3MQ | ||
+ | |s-spec qs=QN7B | ||
|market=Server | |market=Server | ||
|first announced=July 11, 2017 | |first announced=July 11, 2017 | ||
Line 18: | Line 20: | ||
|isa=x86-64 | |isa=x86-64 | ||
|isa family=x86 | |isa family=x86 | ||
− | |microarch=Skylake | + | |microarch=Skylake (server) |
|platform=Purley | |platform=Purley | ||
|chipset=Lewisburg | |chipset=Lewisburg | ||
|core name=Skylake SP | |core name=Skylake SP | ||
|core family=6 | |core family=6 | ||
+ | |core stepping=M0 | ||
|process=14 nm | |process=14 nm | ||
|technology=CMOS | |technology=CMOS | ||
Line 28: | Line 31: | ||
|core count=12 | |core count=12 | ||
|thread count=24 | |thread count=24 | ||
+ | |max memory=768 GiB | ||
|max cpus=2 | |max cpus=2 | ||
− | | | + | |smp interconnect=UPI |
+ | |smp interconnect links=2 | ||
+ | |smp interconnect rate=9.6 GT/s | ||
|tdp=85 W | |tdp=85 W | ||
− | |package | + | |tcase min=0 °C |
+ | |tcase max=76 °C | ||
+ | |package name 1=intel,fclga_3647 | ||
}} | }} | ||
− | '''Xeon Silver 4116T''' is a {{arch|64}} [[dodeca-core]] [[x86]] dual-socket mid-range performance server microprocessor introduced by [[Intel]] in mid-2017. The Silver 4116T, which is based on the server configuration of the {{intel|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]], sports 1 {{x86|AVX-512}} [[FMA]] unit as well as two {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 2.1 GHz with a TDP of 85 W and a {{intel|turbo boost}} frequency of up to 3 GHz, supports up 768 GiB of hexa-channel DDR4-2400 ECC memory. | + | '''Xeon Silver 4116T''' is a {{arch|64}} [[dodeca-core]] [[x86]] dual-socket mid-range performance server microprocessor introduced by [[Intel]] in mid-2017. The Silver 4116T, which is based on the server configuration of the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]], sports 1 {{x86|AVX-512}} [[FMA]] unit as well as two {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 2.1 GHz with a TDP of 85 W and a {{intel|turbo boost}} frequency of up to 3 GHz, supports up 768 GiB of hexa-channel DDR4-2400 ECC memory. |
+ | This specific model (''T'') has 10 years extended life guarantees designed to be [[NEBS]]-friendly for use in [[NEBS]]-complaint applications. | ||
== Cache == | == Cache == | ||
− | {{main|intel/microarchitectures/ | + | {{main|intel/microarchitectures/skylake_(server)#Memory_Hierarchy|l1=Skylake § Cache}} |
{{cache size | {{cache size | ||
|l1 cache=768 KiB | |l1 cache=768 KiB | ||
Line 78: | Line 87: | ||
| pcie config 3 = x4 | | pcie config 3 = x4 | ||
}} | }} | ||
+ | |||
+ | == Features == | ||
+ | {{x86 features | ||
+ | |real=Yes | ||
+ | |protected=Yes | ||
+ | |smm=Yes | ||
+ | |fpu=Yes | ||
+ | |x8616=Yes | ||
+ | |x8632=Yes | ||
+ | |x8664=Yes | ||
+ | |nx=Yes | ||
+ | |mmx=Yes | ||
+ | |emmx=Yes | ||
+ | |sse=Yes | ||
+ | |sse2=Yes | ||
+ | |sse3=Yes | ||
+ | |ssse3=Yes | ||
+ | |sse41=Yes | ||
+ | |sse42=Yes | ||
+ | |sse4a=No | ||
+ | |avx=Yes | ||
+ | |avx2=Yes | ||
+ | |avx512f=Yes | ||
+ | |avx512cd=Yes | ||
+ | |avx512er=No | ||
+ | |avx512pf=No | ||
+ | |avx512bw=Yes | ||
+ | |avx512dq=Yes | ||
+ | |avx512vl=Yes | ||
+ | |avx512ifma=No | ||
+ | |avx512vbmi=No | ||
+ | |avx5124fmaps=No | ||
+ | |avx5124vnniw=No | ||
+ | |avx512vpopcntdq=No | ||
+ | |abm=Yes | ||
+ | |tbm=No | ||
+ | |bmi1=Yes | ||
+ | |bmi2=Yes | ||
+ | |fma3=Yes | ||
+ | |fma4=No | ||
+ | |aes=Yes | ||
+ | |rdrand=Yes | ||
+ | |sha=No | ||
+ | |xop=No | ||
+ | |adx=Yes | ||
+ | |clmul=Yes | ||
+ | |f16c=Yes | ||
+ | |tbt1=No | ||
+ | |tbt2=Yes | ||
+ | |tbmt3=No | ||
+ | |bpt=No | ||
+ | |eist=Yes | ||
+ | |sst=Yes | ||
+ | |flex=No | ||
+ | |fastmem=No | ||
+ | |ivmd=Yes | ||
+ | |intelnode=Yes | ||
+ | |kpt=Yes | ||
+ | |ptt=Yes | ||
+ | |mbe=Yes | ||
+ | |isrt=No | ||
+ | |sba=No | ||
+ | |mwt=No | ||
+ | |sipp=No | ||
+ | |att=No | ||
+ | |ipt=No | ||
+ | |tsx=Yes | ||
+ | |txt=Yes | ||
+ | |ht=Yes | ||
+ | |vpro=Yes | ||
+ | |vtx=Yes | ||
+ | |vtd=No | ||
+ | |ept=Yes | ||
+ | |mpx=No | ||
+ | |sgx=No | ||
+ | |securekey=No | ||
+ | |osguard=No | ||
+ | |3dnow=No | ||
+ | |e3dnow=No | ||
+ | |smartmp=No | ||
+ | |powernow=No | ||
+ | |amdvi=No | ||
+ | |amdv=No | ||
+ | |amdsme=No | ||
+ | |amdtsme=No | ||
+ | |amdsev=No | ||
+ | |rvi=No | ||
+ | |smt=No | ||
+ | |sensemi=No | ||
+ | |xfr=No | ||
+ | }} | ||
+ | |||
+ | == Frequencies == | ||
+ | {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}} | ||
+ | {{frequency table | ||
+ | |freq_base=2,100 MHz | ||
+ | |freq_1=3,000 MHz | ||
+ | |freq_2=3,000 MHz | ||
+ | |freq_3=2,800 MHz | ||
+ | |freq_4=2,800 MHz | ||
+ | |freq_5=2,700 MHz | ||
+ | |freq_6=2,700 MHz | ||
+ | |freq_7=2,700 MHz | ||
+ | |freq_8=2,700 MHz | ||
+ | |freq_9=2,400 MHz | ||
+ | |freq_10=2,400 MHz | ||
+ | |freq_11=2,400 MHz | ||
+ | |freq_12=2,400 MHz | ||
+ | |freq_avx2_base=1,700 MHz | ||
+ | |freq_avx2_1=2,900 MHz | ||
+ | |freq_avx2_2=2,900 MHz | ||
+ | |freq_avx2_3=2,700 MHz | ||
+ | |freq_avx2_4=2,700 MHz | ||
+ | |freq_avx2_5=2,400 MHz | ||
+ | |freq_avx2_6=2,400 MHz | ||
+ | |freq_avx2_7=2,400 MHz | ||
+ | |freq_avx2_8=2,400 MHz | ||
+ | |freq_avx2_9=2,100 MHz | ||
+ | |freq_avx2_10=2,100 MHz | ||
+ | |freq_avx2_11=2,100 MHz | ||
+ | |freq_avx2_12=2,100 MHz | ||
+ | |freq_avx512_base=1,100 MHz | ||
+ | |freq_avx512_1=1,800 MHz | ||
+ | |freq_avx512_2=1,800 MHz | ||
+ | |freq_avx512_3=1,600 MHz | ||
+ | |freq_avx512_4=1,600 MHz | ||
+ | |freq_avx512_5=1,500 MHz | ||
+ | |freq_avx512_6=1,500 MHz | ||
+ | |freq_avx512_7=1,500 MHz | ||
+ | |freq_avx512_8=1,500 MHz | ||
+ | |freq_avx512_9=1,400 MHz | ||
+ | |freq_avx512_10=1,400 MHz | ||
+ | |freq_avx512_11=1,400 MHz | ||
+ | |freq_avx512_12=1,400 MHz | ||
+ | }} | ||
+ | |||
+ | [[Category:microprocessor models by intel based on skylake high core count die]] |
Latest revision as of 18:04, 3 August 2022
Edit Values | |
Xeon Silver 4116T | |
General Info | |
Designer | Intel |
Manufacturer | Intel |
Model Number | 4116T |
Part Number | CD8067303645400 |
S-Spec | SR3MQ QN7B (QS) |
Market | Server |
Introduction | July 11, 2017 (announced) July 11, 2017 (launched) |
Shop | Amazon |
General Specs | |
Family | Xeon Silver |
Series | 4000 |
Locked | Yes |
Frequency | 2,100 MHz |
Turbo Frequency | 3,000 MHz (1 core) |
Clock multiplier | 21 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Skylake (server) |
Platform | Purley |
Chipset | Lewisburg |
Core Name | Skylake SP |
Core Family | 6 |
Core Stepping | M0 |
Process | 14 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 12 |
Threads | 24 |
Max Memory | 768 GiB |
Multiprocessing | |
Max SMP | 2-Way (Multiprocessor) |
Interconnect | UPI |
Interconnect Links | 2 |
Interconnect Rate | 9.6 GT/s |
Electrical | |
TDP | 85 W |
Tcase | 0 °C – 76 °C |
Packaging | |
Package | FCLGA-3647 (FCLGA) |
Dimension | 76.16 mm × 56.6 mm |
Pitch | 0.8585 mm × 0.9906 mm |
Contacts | 3647 |
Socket | Socket P, LGA-3647 |
Xeon Silver 4116T is a 64-bit dodeca-core x86 dual-socket mid-range performance server microprocessor introduced by Intel in mid-2017. The Silver 4116T, which is based on the server configuration of the Skylake microarchitecture and is manufactured on a 14 nm process, sports 1 AVX-512 FMA unit as well as two Ultra Path Interconnect links. This microprocessor, which operates at 2.1 GHz with a TDP of 85 W and a turbo boost frequency of up to 3 GHz, supports up 768 GiB of hexa-channel DDR4-2400 ECC memory.
This specific model (T) has 10 years extended life guarantees designed to be NEBS-friendly for use in NEBS-complaint applications.
Cache[edit]
- Main article: Skylake § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
Integrated Memory Controller
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Expansions[edit]
Expansion Options
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Features[edit]
[Edit/Modify Supported Features]
Frequencies[edit]
- See also: Intel's CPU Frequency Behavior
Mode | Base | Turbo Frequency/Active Cores | |||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|
1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | ||
Normal | 2,100 MHz | 3,000 MHz | 3,000 MHz | 2,800 MHz | 2,800 MHz | 2,700 MHz | 2,700 MHz | 2,700 MHz | 2,700 MHz | 2,400 MHz | 2,400 MHz | 2,400 MHz | 2,400 MHz |
AVX2 | 1,700 MHz | 2,900 MHz | 2,900 MHz | 2,700 MHz | 2,700 MHz | 2,400 MHz | 2,400 MHz | 2,400 MHz | 2,400 MHz | 2,100 MHz | 2,100 MHz | 2,100 MHz | 2,100 MHz |
AVX512 | 1,100 MHz | 1,800 MHz | 1,800 MHz | 1,600 MHz | 1,600 MHz | 1,500 MHz | 1,500 MHz | 1,500 MHz | 1,500 MHz | 1,400 MHz | 1,400 MHz | 1,400 MHz | 1,400 MHz |
Facts about "Xeon Silver 4116T - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon Silver 4116T - Intel#io + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has advanced vector extensions 512 | true + |
has ecc memory support | true + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Extended Page Tables + and Transactional Synchronization Extensions + |
has intel enhanced speedstep technology | true + |
has intel speed shift technology | true + |
has intel trusted execution technology | true + |
has intel turbo boost technology 2 0 | true + |
has intel vpro technology | true + |
has intel vt-x technology | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
l1$ size | 768 KiB (786,432 B, 0.75 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 384 KiB (393,216 B, 0.375 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 384 KiB (393,216 B, 0.375 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 12 MiB (12,288 KiB, 12,582,912 B, 0.0117 GiB) + |
l3$ description | 11-way set associative + |
l3$ size | 16.5 MiB (16,896 KiB, 17,301,504 B, 0.0161 GiB) + |
max memory bandwidth | 107.3 GiB/s (109,875.2 MiB/s, 115.212 GB/s, 115,212.498 MB/s, 0.105 TiB/s, 0.115 TB/s) + |
max memory channels | 6 + |
max pcie lanes | 48 + |
supported memory type | DDR4-2400 + |