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Difference between revisions of "EPYC"

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|-
 
|-
 
! Server <br>([[EPYC]])
 
! Server <br>([[EPYC]])
−
| [[EPYC]] 9006 <br>(Venice)<!--7 Gen--> || [[EPYC]] 9005 <br>9655 (Turin)<!--6 Gen--><hr>9955 (Sorano) <br>(Turin Dense) || [[EPYC]] 8004 <br>(Siena) <hr>[[EPYC]] 9004 <br>(Bergamo) || [[EPYC]] 9004 <br>9124/9654 <br>({{amd|Genoa|l=core}})(-X) || [[EPYC]] 7A53 <br>(Trento) <br>(Badami) || [[EPYC]] 7003 <br>7713/7763 <br>({{amd|Milan|l=core}})(-X) || [[EPYC]] 7002 <br>7452/7532 <br>({{amd|Rome|l=core}}) || N/A || [[EPYC]] 7001 <br>7251/7551 <br>({{amd|Naples|l=core}})  
+
| [[EPYC]] 9006 <br>(Venice) <br>(Venice Classic) <br>(Venice Dense) || [[EPYC]] 9005 <br>(Turin)(-X/-AI) <br>(Turin Dense) <hr>[[EPYC]] 8005 <br>(Sorano, SP6) || [[EPYC]] 9004 <br>(Bergamo) <hr>[[EPYC]] 8004 <br>(Siena, SP6)|| [[EPYC]] 9004 <br>9124/9654 <br>({{amd|Genoa|l=core}})(-X) || [[EPYC]] 7A53 <br>(Trento) <br>(Badami) || [[EPYC]] 7003 <br>7713/7763 <br>([[EPYC]] 7004) <br>({{amd|Milan|l=core}})(-X) || [[EPYC]] 7002 <br>7452/7532 <br>({{amd|Rome|l=core}}) || N/A || [[EPYC]] 7001 <br>7251/7551 <br>({{amd|Naples|l=core}})  
 
|-
 
|-
 
! High-End Desktop <br>([[Ryzen Threadripper]])
 
! High-End Desktop <br>([[Ryzen Threadripper]])
Line 116: Line 116:
  
 
=== AMD EPYC Family ===
 
=== AMD EPYC Family ===
−
 
+
*[https://www.ixbt.com/img/n1/news/2025/4/6/Screenshot_1_large.jpg EPYC series] • [https://wccftech.com/amd-sp7-sp8-platforms-epyc-venice-verano-cpus-12800-mtps-16-channel-memory-128-pcie-6-0-lanes/ SP7/SP8 Platforms]
 +
:• {{amd|Zen 7|l=arch}} • ''Verano'' • EPYC 9007 (SP7) • 2027?
 
{| class="wikitable" cellpadding="3px" style="border: 1px solid black; border-spacing: 0px; width: 100%; text-align:center;"
 
{| class="wikitable" cellpadding="3px" style="border: 1px solid black; border-spacing: 0px; width: 100%; text-align:center;"
 
|-
 
|-
−
! Architecture !! {{amd|Zen 6|l=arch}} !! {{amd|Zen 5|l=arch}} !! {{amd|Zen 5|l=arch}}c !! {{amd|Zen 5|l=arch}} !! {{amd|Zen 4|l=arch}}c !! {{amd|Zen 4|l=arch}}c !! {{amd|Zen 4|l=arch}}<br>V-Cache !! {{amd|Zen 4|l=arch}} !! {{amd|Zen 3|l=arch}} !! {{amd|Zen 3|l=arch}} !! {{amd|Zen 2|l=arch}} !! {{amd|Zen|l=arch}}  
+
! Architecture !! {{amd|Zen 6|l=arch}}c !! {{amd|Zen 6|l=arch}}c !! {{amd|Zen 6|l=arch}} !! {{amd|Zen 5|l=arch}}c !! {{amd|Zen 5|l=arch}} !! {{amd|Zen 5|l=arch}} !! {{amd|Zen 4|l=arch}}c !! {{amd|Zen 4|l=arch}}c !! {{amd|Zen 4|l=arch}}!! {{amd|Zen 4|l=arch}} !! {{amd|Zen 3|l=arch}} !! {{amd|Zen 3|l=arch}} !! {{amd|Zen 2|l=arch}} !! {{amd|Zen|l=arch}}  
 
|-
 
|-
−
! Family <br>Name || {{amd|Venice|l=core}} || {{amd|Turin|l=core}}-X || {{amd|Turin|l=core}} <br>Dense || {{amd|Turin|l=core}} || {{amd|Siena|l=core}} || {{amd|Bergamo|l=core}} || {{amd|Genoa|l=core}}-X || {{amd|Genoa|l=core}} || {{amd|Milan|l=core}}-X || {{amd|Milan|l=core}} || {{amd|Rome|l=core}} || {{amd|Naples|l=core}}  
+
! Family <br>Name || {{amd|Venice|l=core}} <br>Dense || {{amd|Venice|l=core}} <br>Classic || {{amd|Venice|l=core}} || {{amd|Turin|l=core}} <br>Dense || {{amd|Turin|l=core}}-X || {{amd|Turin|l=core}} || {{amd|Siena|l=core}} || {{amd|Bergamo|l=core}} || {{amd|Genoa|l=core}}-X <br>''V-Cache'' || {{amd|Genoa|l=core}} || {{amd|Milan|l=core}}-X || {{amd|Milan|l=core}} || {{amd|Rome|l=core}} || {{amd|Naples|l=core}}  
 
|-
 
|-
 
! Family <br>Branding  
 
! Family <br>Branding  
−
| EPYC 9006 || EPYC 9005 || EPYC 9005 || EPYC 9005 || EPYC 8004 || EPYC 9004 || EPYC 9004 || EPYC 9004 || EPYC 7004 || EPYC 7003 || EPYC 7002 || EPYC 7001  
+
| EPYC 9006 || EPYC 9006 || EPYC 9006 || EPYC 9005 || EPYC 9005 || EPYC 9005 || EPYC 8004 || EPYC 9004 || EPYC 9004 || EPYC 9004 || EPYC 7004 || EPYC 7003 || EPYC 7002 || EPYC 7001  
 
|-
 
|-
 
! Max Core <br>Count  
 
! Max Core <br>Count  
−
| 96 || 128 || 192 || 128 || 64 || 128 || 96 || 96 || 64 || 64 || 64 || 32  
+
| 256 || 128 || 96 || 192 || 128 || 128 || 64 || 128 || 96 || 96 || 64 || 64 || 64 || 32  
 
|-
 
|-
 
! Max Thread <br>Count  
 
! Max Thread <br>Count  
−
| 192 || 256 || 384 || 256 || 128 || 256 || 192 || 192 || 128 || 128 || 128 || 64  
+
| 512 || 256 || 192 || 384 || 256 || 256 || 128 || 256 || 192 || 192 || 128 || 128 || 128 || 64  
 
|-
 
|-
 
! Max L3 <br>Cache  
 
! Max L3 <br>Cache  
−
| TBD || 1536 MB || 384 MB || 384 MB || 256 MB || 256 MB || 1152 MB || 384 MB || 768 MB || 256 MB || 256 MB || 64 MB  
+
| 1024 MB || TBD || 384 MB || 512 MB || 1536 MB || 384 MB || 256 MB || 256 MB || 1152 MB || 384 MB || 768 MB || 256 MB || 256 MB || 64 MB  
 
|-
 
|-
 
! Chiplet <br>Design  
 
! Chiplet <br>Design  
−
| 8x CCD <br>(1x CCX) <br>2x IOD? || 16x CCD <br>(1x CCX) <br>1x IOD || 12x CCD <br>(1x CCX) <br>1x IOD || 16x CCD <br>(1x CCX) <br>1x IOD || 8x CCD <br>(1x CCX) <br>1x IOD || 12x CCD <br>(1x CCX) <br>1x IOD || 12x CCD <br>(1x CCX) <br>1x IOD || 12x CCD <br>(1x CCX) <br>1x IOD || 8x CCD <br>(1x CCX) <br>1x IOD || 8x CCD <br>(1x CCX) <br>1x IOD || 8x CCD <br>(2x CCX) <br>1x IOD || 4x CCD <br>(2x CCX <br>per CCD)  
+
| 8x CCD <br>(1x CCX) <br>2x IOD? <!-- 32Cx CCD --> || 8x CCD <br>(1x CCX) <br>2x IOD? || 8x CCD <br>(1x CCX) <br>2x IOD? || 12x CCD <br>(1x CCX) <br>1x IOD || 16x CCD <br>(1x CCX) <br>1x IOD || 16x CCD <br>(1x CCX) <br>1x IOD || 8x CCD <br>(1x CCX) <br>1x IOD || 16x CCD <br>(1x CCX) <br>1x IOD || 12x CCD <br>(1x CCX) <br>1x IOD || 12x CCD <br>(1x CCX) <br>1x IOD || 8x CCD <br>(1x CCX) <br>1x IOD || 8x CCD <br>(1x CCX) <br>1x IOD || 8x CCD <br>(2x CCX) <br>1x IOD || 4x CCD <br>(2x CCX <br>per CCD)  
 
|-
 
|-
 
! Memory <br>Support  
 
! Memory <br>Support  
−
| DDR5-XXXX? || DDR5-6000? || DDR5-6400 || DDR5-6400 || DDR5-5200 || DDR5-5600 || DDR5-4800 || DDR5-4800 || DDR4-3200 || DDR4-3200 || DDR4-3200 || DDR4-2666  
+
| DDR5-6400 || DDR5-6400 || DDR5-6400 || DDR5-6000 || DDR5-6000 || DDR5-6000 || DDR5-5200 || DDR5-5600 || DDR5-4800 || DDR5-4800 || DDR4-3200 || DDR4-3200 || DDR4-3200 || DDR4-2666  
 
|-
 
|-
 
! Memory <br>Channels  
 
! Memory <br>Channels  
−
| 16 Channel <br>(SP7) || 12 Channel <br>(SP5) || 12 Channel || 12 Channel || 6 Channel || 12 Channel || 12 Channel || 12 Channel || 8 Channel || 8 Channel || 8 Channel || 8 Channel  
+
| 16 Channel || 16 Channel || 4/8 Channel || 12 Channel || 12 Channel || 12 Channel || 6 Channel || 12 Channel || 12 Channel || 12 Channel || 8 Channel || 8 Channel || 8 Channel || 8 Channel  
 
|-
 
|-
 
! PCIe Gen <br>Support  
 
! PCIe Gen <br>Support  
−
| TBD || TBD || 128 Gen 5 || 128 Gen 5 || 96 Gen 5 || 128 Gen 5 || 128 Gen 5 || 128 Gen 5 || 128 Gen 4 || 128 Gen 4 || 128 Gen 4 || 64 Gen 3  
+
| 96/128 <br>Gen 6 || 96/128 <br>Gen 6 || 128/192 <br>Gen 6 || 128 <br>Gen 5 || 128 <br>Gen 5 || 128 <br>Gen 5 || 96 <br>Gen 5 || 128 <br>Gen 5 || 128 <br>Gen 5 || 128 <br>Gen 5 || 128 <br>Gen 4 || 128 <br>Gen 4 || 128 <br>Gen 4 || 64 <br>Gen 3  
 
|-
 
|-
 
! TDP (Max)  
 
! TDP (Max)  
−
| ~600W || 500W <br>(cTDP <br>600W) || 500W <br>(cTDP <br>450W) || 400W <br>(cDP <br>320W) || 70W -<br>225W || 320W <br>(cTDP <br>400W) || 400W || 400W || 280W || 280W || 280W || 200W  
+
| ~600W || TBD || ~500W || 500W <br>(cTDP <br>450W) || 500W <br>(cTDP <br>600W) || 400W <br>(cTDP <br>320W) || 70W -<br>225W || 320W <br>(cTDP <br>400W) || 400W || 400W || 280W || 280W || 280W || 200W  
 
|-
 
|-
 
! Platform  
 
! Platform  
−
| SP7 || SP5 || SP5 || SP5 || SP6 || SP5 || SP5 || SP5 || SP3 || SP3 || SP3 || SP3  
+
| SP7 || SP7 || SP8 || SP5 || SP5 || SP5 || SP6 || SP5 || SP5 || SP5 || SP3 || SP3 || SP3 || SP3  
 
|-
 
|-
 
! Socket  
 
! Socket  
−
| TBD || LGA 6096<br>(SP5) || LGA 6096<br>(SP5) || LGA 6096 || LGA 4844 || LGA 6096 || LGA 6096 || LGA 6096 || LGA 4094 || LGA 4094 || LGA 4094 || LGA 4094  
+
| TBD || TBD || TBD || LGA 6096 || LGA 6096 || LGA 6096 || LGA 4844 || LGA 6096 || LGA 6096 || LGA 6096 || LGA 4094 || LGA 4094 || LGA 4094 || LGA 4094  
 
|-
 
|-
 
! Process <br>Node  
 
! Process <br>Node  
−
| 2nm TSMC || 4nm TSMC || 3nm TSMC || 4nm TSMC || 5nm TSMC || 4nm TSMC || 5nm TSMC || 5nm TSMC || 7nm TSMC || 7nm TSMC || 7nm TSMC || 14nm <br>GloFo  
+
| 2nm TSMC || 2nm TSMC || 2nm TSMC || 3nm TSMC || 4nm TSMC || 4nm TSMC || 5nm TSMC || 4nm TSMC || 5nm TSMC || 5nm TSMC || 7nm TSMC || 7nm TSMC || 7nm TSMC || 14nm <br>GloFo  
 
|-
 
|-
 
! Launch  
 
! Launch  
−
| 2026? || 2025 || 2025 || 2024 || 2023 || 2023 || 2023 || 2022 || 2022 || 2021 || 2019 || 2017  
+
| 2026? || 2026? || 2026? || 2025 || 2025 || 2024 || 2023 || 2023 || 2023 || 2022 || 2022 || 2021 || 2019 || 2017  
 
|-
 
|-
 
|}
 
|}
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| 2021  
 
| 2021  
 
| {{amd|Milan|l=core}}
 
| {{amd|Milan|l=core}}
−
| rowspan="2" | 7003 series
+
| 7003 series
 
| rowspan="2" | 64× {{amd|Zen 3|l=arch}}
 
| rowspan="2" | 64× {{amd|Zen 3|l=arch}}
 
|-
 
|-
−
| rowspan="2" | 2022
+
| 2022
 
| {{amd|Milan|l=core}}-X
 
| {{amd|Milan|l=core}}-X
 +
| 7004 series
 
|-
 
|-
 
| rowspan="5" | 4th
 
| rowspan="5" | 4th
 +
| 2022
 
| {{amd|Genoa|l=core}}
 
| {{amd|Genoa|l=core}}
 
| rowspan="3" | 9004 series
 
| rowspan="3" | 9004 series
 
| rowspan="2" | 96× {{amd|Zen 4|l=arch}}
 
| rowspan="2" | 96× {{amd|Zen 4|l=arch}}
 
| rowspan="3" | {{amd|SP5|Socket SP5|l=package}} (LGA)
 
| rowspan="3" | {{amd|SP5|Socket SP5|l=package}} (LGA)
−
| rowspan="8" | DDR5
+
| rowspan="5" | DDR5
 
|-
 
|-
 
| rowspan="3" | 2023
 
| rowspan="3" | 2023
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|-
 
|-
 
| 2024
 
| 2024
−
| {{amd|Raphael|l=core}}
+
| {{amd|Raphael|l=core}}-X
 
| 4004 series
 
| 4004 series
 
| 16× {{amd|Zen 4|l=arch}}
 
| 16× {{amd|Zen 4|l=arch}}
 
| {{amd|AM5|Socket AM5|l=package}} (LGA)
 
| {{amd|AM5|Socket AM5|l=package}} (LGA)
 
|-
 
|-
−
| rowspan="3" | 5th
+
| rowspan="4" | 5th
−
| rowspan="2" | 2024
+
| rowspan="3" | 2024
−
| {{amd|Turin|l=core}}
+
| {{amd|Turin|l=core}} (-X)
 
| rowspan="2" | 9005 series
 
| rowspan="2" | 9005 series
 
| 128× {{amd|Zen 5|l=arch}}
 
| 128× {{amd|Zen 5|l=arch}}
 
| rowspan="2" | {{amd|SP5|Socket SP5|l=package}} (LGA)
 
| rowspan="2" | {{amd|SP5|Socket SP5|l=package}} (LGA)
 +
| rowspan="4" | DDR5
 
|-
 
|-
 
| {{amd|Turin|l=core}} Dense
 
| {{amd|Turin|l=core}} Dense
 
| 192× {{amd|Zen 5|l=arch}}c
 
| 192× {{amd|Zen 5|l=arch}}c
 +
|-
 +
| {{amd|Sorano|l=core}}
 +
| 8005 series
 +
| 64× {{amd|Zen 5|l=arch}}c
 +
| {{amd|SP6|Socket SP6|l=package}} (LGA)
 
|-
 
|-
 
| 2025
 
| 2025
Line 240: Line 249:
 
| {{amd|AM5|Socket AM5|l=package}} (LGA)
 
| {{amd|AM5|Socket AM5|l=package}} (LGA)
 
|-
 
|-
−
| 6th
+
| rowspan="3" | 6th
−
| 2026
+
| rowspan="3" | 2026
 
| {{amd|Venice|l=core}}
 
| {{amd|Venice|l=core}}
−
| 9006 series
+
| rowspan="3" | 9006 series
 
| 96× {{amd|Zen 6|l=arch}}
 
| 96× {{amd|Zen 6|l=arch}}
 +
| {{amd|SP7|Socket SP8|l=package}} (LGA)
 +
| rowspan="3" | DDR5/6
 +
|-
 +
| {{amd|Venice|l=core}} Classic
 +
| 128× {{amd|Zen 6|l=arch}}c
 +
| rowspan="2" | {{amd|SP7|Socket SP7|l=package}} (LGA)
 +
|-
 +
| {{amd|Venice|l=core}} Dense
 +
| 256× {{amd|Zen 6|l=arch}}c
 +
|-
 +
| 7st
 +
| 2027
 +
| {{amd|Verano|l=core}}
 +
| 9007 series
 +
| 256× {{amd|Zen 7|l=arch}}
 
| {{amd|SP7|Socket SP7|l=package}} (LGA)
 
| {{amd|SP7|Socket SP7|l=package}} (LGA)
−
| DDR5 ?
+
| DDR5/6
 
|-
 
|-
 
! colspan="7" | Embedded
 
! colspan="7" | Embedded
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| rowspan="2" | 5th
 
| rowspan="2" | 5th
 
| rowspan="2" | 2025
 
| rowspan="2" | 2025
−
| {{amd|Turin|l=core}}
+
| {{amd|Turin|l=core}} (-X)
 
| rowspan="2" | Embedded 9005 series
 
| rowspan="2" | Embedded 9005 series
 
| 128× {{amd|Zen 5|l=arch}}
 
| 128× {{amd|Zen 5|l=arch}}
Line 301: Line 325:
 
|}
 
|}
  
 +
==[[AMD]] EPYC series==
 +
*{{amd|EPYC}}
 +
 +
{| border="0" cellpadding="5" width="90%"
 +
|-
 +
|width="30%" valign="top" align="left"|
 +
===EPYC 7001 series===
 +
:; EPYC 7001 (Naples)
 +
:• Zen microarchitecture
 +
:» 14 nm (0.014 micron)
 +
:» Server SoC
 +
:» Up to 32 cores
 +
:» Up to 3.1 GHz
 +
:» Up to 16 MB L2 cache
 +
:» Up to 64 MB L3 cache
 +
:» 64-bit
 +
:» AVX2, FMA3 instructions
 +
:» Virtualization
 +
:» Simultaneous multi-threading
 +
:» Frequency boost
 +
:» No integrated GPU
 +
:» Up to 2-way processing
 +
:• Socket SP3
 +
|width="30%" valign="top" align="left"|
 +
===EPYC 7002 series===
 +
:; EPYC 7002 (Rome)
 +
:•  Zen 2 microarchitecture
 +
:» 7 nm (0.007 micron)
 +
:» Server SoC
 +
:» Up to 64 cores
 +
:» Up to 3.7 GHz
 +
:» Up to 32 MB L2 cache
 +
:» Up to 256 MB L3 cache
 +
:» 64-bit
 +
:» AVX2, FMA3 instructions
 +
:» Virtualization
 +
:» Simultaneous multi-threading
 +
:» Frequency boost
 +
:» No integrated GPU
 +
:» Up to 2-way processing
 +
:• Socket SP3
 +
|width="30%" valign="top" align="left"|
 +
===EPYC 7003/7004 series===
 +
:;EPYC 7003/7004 (Milan/Milan-X)
 +
:• Zen 3 microarchitecture
 +
:» 7 nm (0.007 micron)
 +
:» Server SoC
 +
:» Up to 64 cores
 +
:» Up to 3.7 GHz
 +
:» Up to 32 MB L2 cache
 +
:» Up to 256/768 MB L3 cache
 +
:» 64-bit
 +
:» AVX2, FMA3 instructions
 +
:» Virtualization
 +
:» Simultaneous multi-threading
 +
:» Frequency boost
 +
:» No integrated GPU
 +
:» High and very high power
 +
:» Up to 2-way processing
 +
:• Socket SP3
 +
|}
 +
 +
{| border="0" cellpadding="5" width="90%"
 +
|-
 +
|width="30%" valign="top" align="left"|
 +
===EPYC 8004 series===
 +
:;EPYC 8004 (Siena)
 +
:• Zen 4c microarchitecture
 +
:» 5 nm (0.005 micron)
 +
:» Server SoC
 +
:» Up to 64 cores
 +
:» Up to 2.65 GHz
 +
:» Up to 128/256 MB L3 cache
 +
:» 64-bit
 +
:» FMA3, AVX512 instructions
 +
:» Virtualization
 +
:» Simultaneous multi-threading
 +
:» Frequency boost
 +
:» No integrated GPU
 +
:» Standard and high power
 +
:» 1-way processing
 +
:• Socket SP6
 +
|width="30%" valign="top" align="left"|
 +
===EPYC 9004 series===
 +
:;EPYC 9004 (Genoa/Genoa-X/Bergamo)
 +
:• Zen 4/4c microarchitecture
 +
:» 5 nm (0.005 micron)
 +
:» Server SoC
 +
:» Up to 128 cores
 +
:» Up to 4.1 GHz
 +
:» Up to 128 MB L2 cache
 +
:» Up to 384/1152 MB L3 cache
 +
:» 64-bit
 +
:» FMA3, AVX512 instructions
 +
:» Virtualization
 +
:» Simultaneous multi-threading
 +
:» Frequency boost
 +
:» No integrated GPU
 +
:» High to ultra high power
 +
:» Up to 2-way processing
 +
:• Socket SP5
 +
|width="30%" valign="top" align="left"|
 +
===EPYC Embedded 9004===
 +
:;EPYC 9004 (Genoa)
 +
:• Zen 4 microarchitecture
 +
:» 5 nm (0.005 micron)
 +
:» Embedded SoC
 +
:» Up to 96 cores
 +
:» Up to 3.25 GHz
 +
:» Up to 96 MB L2 cache
 +
:» Up to 384 MB L3 cache
 +
:» 64-bit
 +
:» FMA3, AVX512 instructions
 +
:» Virtualization
 +
:» Simultaneous multi-threading
 +
:» Frequency boost
 +
:» No integrated GPU
 +
:» High to ultra high power
 +
:» Up to 2-way processing
 +
:• Socket SP5
 +
|}
 +
 +
{| border="0" cellpadding="5" width="90%"
 +
|-
 +
|width="30%" valign="top" align="left"|
 +
===EPYC 9005 series===
 +
:;EPYC 9005 (Turin/Turin Dense)
 +
:• Zen 5/5c microarchitecture
 +
:» 3 nm/4 nm (0.003/0.004 micron)
 +
:» Server SoC
 +
:» Up to 96/192 cores
 +
:» Up to 4.2 GHz
 +
:» Up to 192 MB L2 cache
 +
:» Up to 512 MB L3 cache
 +
:» 64-bit
 +
:» FMA3, AVX512 instructions
 +
:» Virtualization
 +
:» Simultaneous multi-threading
 +
:» Frequency boost
 +
:» No integrated GPU
 +
:» High and ultra high power
 +
:» Up to 2-way processing
 +
:• Socket SP5
 +
|width="30%" valign="top" align="left"|
 +
===EPYC Embedded 9005===
 +
:;EPYC 9005 (Turin/Turin Dense)
 +
:• Zen 5/5c microarchitecture
 +
:» 3 nm/4 nm (0.003/0.004 micron)
 +
:» Embedded SoC
 +
:» Up to 192 cores
 +
:» Up to 3.65 GHz
 +
:» Up to 192 MB L2 cache
 +
:» Up to 512 MB L3 cache
 +
:» 64-bit
 +
:» FMA3, AVX512 instructions
 +
:» Virtualization
 +
:» Simultaneous multi-threading
 +
:» Frequency boost
 +
:» No integrated GPU
 +
:» High to ultra high power
 +
:» Up to 2-way processing
 +
:• Socket SP5
 +
|width="30%" valign="top" align="left"|
 +
===EPYC 9006 series===
 +
:;EPYC 9006 (Venice/Venice Dense)
 +
:• Zen 6/6c microarchitecture
 +
:» 2 nm/3 nm (0.002/0.003 micron)
 +
:» Server SoC
 +
:» Up to 96/256 cores
 +
:» Up to 4.2 GHz
 +
:» Up to 192 MB L2 cache
 +
:» Up to 512 MB L3 cache
 +
:» 64-bit
 +
:» FMA3, AVX512 instructions
 +
:» Virtualization
 +
:» Simultaneous multi-threading
 +
:» Frequency boost
 +
:» No integrated GPU
 +
:» High and ultra high power
 +
:» Up to 2-way processing
 +
:• Socket SP7
 +
|}
 +
 +
*EPYC 9005 "Turin" (Zen 5): 96 Cores / 192 Threads / 16 CCDs
 +
*EPYC 9005 "Turin Dense" (Zen 5c): 192 Cores / 384 Threads / 12 CCDs
 +
*EPYC 9006 "Venice" (Zen 6): 96 Cores / 192 Threads / 8 CCDs
 +
*EPYC 9006 "Venice Dense" (Zen 6c): 256 Cores / 512 Threads / 8 CCDs
 +
 +
{| border="0" cellpadding="5" width="90%"
 +
|-
 +
|width="30%" valign="top" align="left"|
 +
===EPYC 4004 series===
 +
:;EPYC 4004 (Raphael-R)
 +
:• Zen 4 microarchitecture
 +
:» 5 nm (0.005 micron)
 +
:» Entry-level server SoC
 +
:» Up to 16 cores
 +
:» Up to 4.5 GHz
 +
:» Up to 16 MB L2 cache
 +
:» Up to 128 MB L3 cache
 +
:» 64-bit
 +
:» FMA3, AVX512 instructions
 +
:» Virtualization
 +
:» Simultaneous multi-threading
 +
:» Frequency boost
 +
:» Integrated graphics
 +
:» Medium to high power
 +
:» 1-way processing
 +
:• Socket AM5
 +
|width="30%" valign="top" align="left"|
 +
===EPYC 4005 series===
 +
:;EPYC 4005 (Grado)
 +
:• Zen 5 microarchitecture
 +
:» 3 nm (0.003 micron)
 +
:» Entry-level server SoC
 +
:» Up to 16 cores
 +
:» Up to 4.3 GHz
 +
:» Up to 16 MB L2 cache
 +
:» Up to 128 MB L3 cache
 +
:» 64-bit
 +
:» FMA3, AVX512 instructions
 +
:» Virtualization
 +
:» Simultaneous multi-threading
 +
:» Frequency boost
 +
:» Integrated graphics
 +
:» Medium and high power
 +
:» 1-way processing
 +
:• Socket AM5
 +
|width="30%" valign="top" align="left"|
 +
===EPYC 4006 series===
 +
:;EPYC 4006 (Weisshorn)
 +
:• Zen 6 microarchitecture
 +
:» 3 nm (0.003 micron)
 +
:» Entry-level server SoC
 +
:» Up to 16 cores
 +
:» Up to 4.3 GHz
 +
:» Up to 16 MB L2 cache
 +
:» Up to 128 MB L3 cache
 +
:» 64-bit
 +
:» FMA3, AVX512 instructions
 +
:» Virtualization
 +
:» Simultaneous multi-threading
 +
:» Frequency boost
 +
:» Integrated graphics
 +
:» Medium and high power
 +
:» 1-way processing
 +
:• Socket AM5
 +
|}
  
 
[[Category:amd]]
 
[[Category:amd]]

Latest revision as of 23:33, 2 October 2025


Overview[edit]

Codenames[edit]

Microarchitecture Codename Socket Process Cores/Threads
(Cx CCD) 		Introduction
Zen Raven Ridge • Summit Ridge
Whitehaven • Naples 		Socket SP3 14 nm 32C/64T
(4x CCD) 		June, 2017
Zen+ Picasso • Colfax • Dali
Pinnacle Ridge • Naples 		Socket SP3 14 nm 8-32 June, 2017
Zen 2 Renoir • Matisse • Lucienne
Castle Peak • Rome 		Socket SP3 7 nm 64C/128T
(8x CCD) 		August, 2019
Zen 3 Cezanne • Vermeer
Chagall • Milan(-X) 		Socket SP3 7 nm+ 64C/128T
(8x CCD) 		March, 2021
Zen 4 (Persephone)
(CCD Durango) 		Raphael • Phoenix (APU)
Storm Peak • Hawk Point
Dragon Range • Genoa(-X) 		Socket SP5
Socket AM5 		5 nm 96C/192T November, 2022
Zen 4c (Dionysus)
(CCD Vindhya) 		Phoenix 2 (APU)
Bergamo • Siena 		Socket SP5
Socket SP6 		5 nm 128C/256T November, 2022
Zen 5 (Nirvana)
(CCD Eldora) 		Granite Ridge • Strix Point
Turin • Turin Dense 		Socket SP5
Socket AM5 		4 nm 96C/192T
(16x CCD) 		November, 2023
Zen 5c (Prometheus) Granite Ridge • Strix Point
Turin • Turin Dense 		Socket SP5 3 nm 192C/384T
(12x CCD) 		November, 2023
Zen 6 (Morpheus) Venice • Medusa Socket SP5 3 nm 96C/192T
(8x CCD) 		July, 2024
Zen 6c (Monarch) Venice Dense • Medusa Socket SP5 2 nm 256C/512T
(8x CCD) 		July, 2024
  • EPYC 9005 "Turin" (Zen 5): 96 Cores / 192 Threads / 16 CCDs
  • EPYC 9005 "Turin Dense" (Zen 5c): 192 Cores / 384 Threads / 12 CCDs
  • EPYC 9006 "Venice" (Zen 6): 96 Cores / 192 Threads / 8 CCDs
  • EPYC 9006 "Venice Dense" (Zen 6c): 256 Cores / 512 Threads / 8 CCDs


AMD Zen Series[edit]

AMD • AMD Zen • AMD Ryzen • AMD EPYC
AMD Ryzen
AMD Zen 		Server PC • Desktop Mobile • Tablet Embedded
Threadripper Mainstream Elite Premium Mainstream
Zen Naples
(EPYC 7001)
Snowy Owl
(EPYC 3001) 		Whitehaven
(Ryzen 1000) 		Summit Ridge
(Ryzen 1000) 		Raven Ridge
(Ryzen 2000) 		Dali (Athlon) Banded Kestrel
(R1000 series)
Great Horned Owl
(V1000 series)
Zen+ Colfax
(Ryzen 2000) 		Pinnacle Ridge
(Ryzen 2000) 		Picasso
(Ryzen 3000) 		Pollock River Hawk
Zen 2
(Valhalla)
(CCD Aspen
Highlands) 		Rome
(EPYC 7002) 		Castle Peak (Pro)
(Ryzen 3000) 		Matisse
(Ryzen 3000) 		Renoir
(Ryzen 4000) 		Mendocino
(Athlon, 7000)
Lucienne
(Ryzen 7000) 		Grey Hawk
(V2000 series)
Zen 3
(Cerberus)
(CCD Brecken
Ridge) 		Milan
Milan-X
(EPYC 7003) 		Chagall
(Ryzen 5000) 		Vermeer
Vermeer-X
(Ryzen 5000) 		Cezanne
(Ryzen 5000) 		Barcelo
(Ryzen 5000)
Barcelo-R
(Ryzen 7000) 		Ryzen
(V3000 series)
Zen 3+ Rembrandt
(Ryzen 6000)
Rembrandt-R
(Ryzen 7000)
Zen 4
(Persephone)
(CCD Durango) 		Genoa
Genoa-X
(EPYC 9004) 		Storm Peak
(Ryzen 7000) 		Raphael
Raphael-X
(Ryzen 7000) 		Dragon Range
Dragon Range-X
(Ryzen 7000) 		Hawk Point
(Ryzen 8000)
Phoenix (APU)
(Ryzen 7000) 		Escher
(Ryzen)
Zen 4c
(Dionysus)
(CCD Vindhya) 		Bergamo
(EPYC 9004)
Siena
(EPYC 8004) 		Phoenix 2 (APU)
(Ryzen 8000, Z1)
Zen 5
(Nirvana)
(CCD Eldora)
Zen 5c
(Prometheus) 		Turin
(EPYC 9005)
Turin Dense
(Sorano) 		Shimada Peak
(Ryzen 9000) 		Granite Ridge
(Ryzen 9000)
Weisshorn		 Fire Range
(Ryzen 9000)
Strix Halo
(Ryzen AI 300) 		Krackan Point
(Ryzen AI 300)
Strix Point
(Ryzen AI 300) 		Sonoma Valley
(Ryzen APU)
Bald Eagle
Point
Zen 6
(Morpheus)
Zen 6c
(Monarch) 		Venice
(EPYC 9006) 		Medusa

AMD Ryzen Family[edit]

Zen Family
Core
Architecture 		Zen 6/6c Zen 5/5c Zen 4c Zen 4 Zen 3+ Zen 3 Zen 2 Zen+ Zen
Core
Codename 		Morpheus
Monarch 		Nirvana
Prometheus 		Dionysus Persephone Warhol Cerberus Valhalla Zen+ Zen
CCD
Codename 		TBA Eldora Vindhya Durango TBC Breken
Ridge 		Aspen
Highlands 		N/A N/A
Server
(EPYC) 		EPYC 9006
(Venice)
(Venice Classic)
(Venice Dense) 		EPYC 9005
(Turin)(-X/-AI)
(Turin Dense)
EPYC 8005
(Sorano, SP6) 		EPYC 9004
(Bergamo)
EPYC 8004
(Siena, SP6)		 EPYC 9004
9124/9654
(Genoa)(-X) 		EPYC 7A53
(Trento)
(Badami) 		EPYC 7003
7713/7763
(EPYC 7004)
(Milan)(-X) 		EPYC 7002
7452/7532
(Rome) 		N/A EPYC 7001
7251/7551
(Naples)
High-End Desktop
(Ryzen Threadripper) 		Ryzen 10000
(Medusa) 		Ryzen 9000
(Shimada Peak) 		TBA Ryzen 7000
(Storm Peak) 		N/A Ryzen 5000
(Chagall) 		Ryzen 3000
(Castle Peak) 		Ryzen 2000
(Colfax) 		Ryzen 1000
(Whitehaven)
Mainstream
Desktop 		Ryzen 10000
(Olympic Ridge)
EPYC 4006
(Weisshorn) 		Ryzen 9000
(Granite Ridge)
EPYC 4005
(Grado) 		TBA Ryzen 7000
(Raphael)
EPYC 4004
(Raphael-R) 		Ryzen 6000
(Warhol) 		Ryzen 5000
(Vermeer) 		Ryzen 3000
(Matisse) 		Ryzen 2000
(Pinnacle
Ridge) 		Ryzen 1000
(Summit
Ridge)
Mainstream
Notebook (APU) 		Ryzen AI 500
(Medusa Point) 		Ryzen AI 300
(Strix Point)
Ryzen AI 300
(Krackan Point) 		Ryzen Z1
(Phoenix 2)
Ryzen 8000
(Hawk Point) 		Ryzen 8000
(Phoenix)
Ryzen 7000
(Dragon Range) 		Ryzen 6000
(Rembrandt)
Ryzen 7000
(Rembrandt-R) 		Ryzen 5000
(Cezanne) 		Ryzen 4000
(Renoir) 		Ryzen 3000
(Picasso) 		Ryzen 2000
(Raven
Ridge)
Low-Power
Mobile 		Ryzen AI 500
(Sound Wave) 		Ryzen AI 400
(Sonoma Valley)
AI 400 (Bald
Eagle Point) 		TBA Ryzen 8000
(Escher) 		TBA Ryzen 6000
(Barcelo) 		Ryzen 5000
(Lucienne)
Athlon, 7000
(Mendocino) 		Athlon
(Pollock) 		Athlon
(Dali)
Process Node 3 nm/2 nm 4 nm/3 nm 5 nm/4 nm 5 nm/4 nm 6 nm 7 nm 7 nm 12 nm 14 nm

AMD EPYC Family[edit]

• Zen 7 • Verano • EPYC 9007 (SP7) • 2027?
Architecture Zen 6c Zen 6c Zen 6 Zen 5c Zen 5 Zen 5 Zen 4c Zen 4c Zen 4 Zen 4 Zen 3 Zen 3 Zen 2 Zen
Family
Name 		Venice
Dense 		Venice
Classic 		Venice Turin
Dense 		Turin-X Turin Siena Bergamo Genoa-X
V-Cache 		Genoa Milan-X Milan Rome Naples
Family
Branding 		EPYC 9006 EPYC 9006 EPYC 9006 EPYC 9005 EPYC 9005 EPYC 9005 EPYC 8004 EPYC 9004 EPYC 9004 EPYC 9004 EPYC 7004 EPYC 7003 EPYC 7002 EPYC 7001
Max Core
Count 		256 128 96 192 128 128 64 128 96 96 64 64 64 32
Max Thread
Count 		512 256 192 384 256 256 128 256 192 192 128 128 128 64
Max L3
Cache 		1024 MB TBD 384 MB 512 MB 1536 MB 384 MB 256 MB 256 MB 1152 MB 384 MB 768 MB 256 MB 256 MB 64 MB
Chiplet
Design 		8x CCD
(1x CCX)
2x IOD? 		8x CCD
(1x CCX)
2x IOD? 		8x CCD
(1x CCX)
2x IOD? 		12x CCD
(1x CCX)
1x IOD 		16x CCD
(1x CCX)
1x IOD 		16x CCD
(1x CCX)
1x IOD 		8x CCD
(1x CCX)
1x IOD 		16x CCD
(1x CCX)
1x IOD 		12x CCD
(1x CCX)
1x IOD 		12x CCD
(1x CCX)
1x IOD 		8x CCD
(1x CCX)
1x IOD 		8x CCD
(1x CCX)
1x IOD 		8x CCD
(2x CCX)
1x IOD 		4x CCD
(2x CCX
per CCD)
Memory
Support 		DDR5-6400 DDR5-6400 DDR5-6400 DDR5-6000 DDR5-6000 DDR5-6000 DDR5-5200 DDR5-5600 DDR5-4800 DDR5-4800 DDR4-3200 DDR4-3200 DDR4-3200 DDR4-2666
Memory
Channels 		16 Channel 16 Channel 4/8 Channel 12 Channel 12 Channel 12 Channel 6 Channel 12 Channel 12 Channel 12 Channel 8 Channel 8 Channel 8 Channel 8 Channel
PCIe Gen
Support 		96/128
Gen 6 		96/128
Gen 6 		128/192
Gen 6 		128
Gen 5 		128
Gen 5 		128
Gen 5 		96
Gen 5 		128
Gen 5 		128
Gen 5 		128
Gen 5 		128
Gen 4 		128
Gen 4 		128
Gen 4 		64
Gen 3
TDP (Max) ~600W TBD ~500W 500W
(cTDP
450W) 		500W
(cTDP
600W) 		400W
(cTDP
320W) 		70W -
225W 		320W
(cTDP
400W) 		400W 400W 280W 280W 280W 200W
Platform SP7 SP7 SP8 SP5 SP5 SP5 SP6 SP5 SP5 SP5 SP3 SP3 SP3 SP3
Socket TBD TBD TBD LGA 6096 LGA 6096 LGA 6096 LGA 4844 LGA 6096 LGA 6096 LGA 6096 LGA 4094 LGA 4094 LGA 4094 LGA 4094
Process
Node 		2nm TSMC 2nm TSMC 2nm TSMC 3nm TSMC 4nm TSMC 4nm TSMC 5nm TSMC 4nm TSMC 5nm TSMC 5nm TSMC 7nm TSMC 7nm TSMC 7nm TSMC 14nm
GloFo
Launch 2026? 2026? 2026? 2025 2025 2024 2023 2023 2023 2022 2022 2021 2019 2017

AMD EPYC CPU Generations[edit]

AMD EPYC CPU Generations
Gen Year Codename Product line Cores Socket Memory
Server
1st 2017 Naples 7001 series 32× Zen Socket SP3 (LGA) DDR4
2nd 2019 Rome 7002 series 64× Zen 2
3rd 2021 Milan 7003 series 64× Zen 3
2022 Milan-X 7004 series
4th 2022 Genoa 9004 series 96× Zen 4 Socket SP5 (LGA) DDR5
2023 Genoa-X
Bergamo 128× Zen 4c
Siena 8004 series 64× Zen 4c Socket SP6 (LGA)
2024 Raphael-X 4004 series 16× Zen 4 Socket AM5 (LGA)
5th 2024 Turin (-X) 9005 series 128× Zen 5 Socket SP5 (LGA) DDR5
Turin Dense 192× Zen 5c
Sorano 8005 series 64× Zen 5c Socket SP6 (LGA)
2025 Grado 4005 series 16× Zen 5 Socket AM5 (LGA)
6th 2026 Venice 9006 series 96× Zen 6 Socket SP8 (LGA) DDR5/6
Venice Classic 128× Zen 6c Socket SP7 (LGA)
Venice Dense 256× Zen 6c
7st 2027 Verano 9007 series 256× Zen 7 Socket SP7 (LGA) DDR5/6
Embedded
1st 2018 Snowy Owl Embedded 3001 series 16× Zen Package SP4 (BGA) DDR4
2019 Naples Embedded 7001 series 32× Zen Socket SP3 (LGA)
2nd 2021 Rome Embedded 7002 series 64× Zen 2
3rd 2022 Milan Embedded 7003 series 64× Zen 3
4th 2023 Genoa Embedded 9004 series 96× Zen 4 Socket SP5 (LGA) DDR5
Siena Embedded 8004 series 64× Zen 4c Socket SP6 (LGA)
5th 2025 Turin (-X) Embedded 9005 series 128× Zen 5 Socket SP5 (LGA)
Turin Dense 192× Zen 5c

AMD EPYC series[edit]

EPYC 7001 series[edit]

EPYC 7001 (Naples)
• Zen microarchitecture
» 14 nm (0.014 micron)
» Server SoC
» Up to 32 cores
» Up to 3.1 GHz
» Up to 16 MB L2 cache
» Up to 64 MB L3 cache
» 64-bit
» AVX2, FMA3 instructions
» Virtualization
» Simultaneous multi-threading
» Frequency boost
» No integrated GPU
» Up to 2-way processing
• Socket SP3

EPYC 7002 series[edit]

EPYC 7002 (Rome)
• Zen 2 microarchitecture
» 7 nm (0.007 micron)
» Server SoC
» Up to 64 cores
» Up to 3.7 GHz
» Up to 32 MB L2 cache
» Up to 256 MB L3 cache
» 64-bit
» AVX2, FMA3 instructions
» Virtualization
» Simultaneous multi-threading
» Frequency boost
» No integrated GPU
» Up to 2-way processing
• Socket SP3

EPYC 7003/7004 series[edit]

EPYC 7003/7004 (Milan/Milan-X)
• Zen 3 microarchitecture
» 7 nm (0.007 micron)
» Server SoC
» Up to 64 cores
» Up to 3.7 GHz
» Up to 32 MB L2 cache
» Up to 256/768 MB L3 cache
» 64-bit
» AVX2, FMA3 instructions
» Virtualization
» Simultaneous multi-threading
» Frequency boost
» No integrated GPU
» High and very high power
» Up to 2-way processing
• Socket SP3

EPYC 8004 series[edit]

EPYC 8004 (Siena)
• Zen 4c microarchitecture
» 5 nm (0.005 micron)
» Server SoC
» Up to 64 cores
» Up to 2.65 GHz
» Up to 128/256 MB L3 cache
» 64-bit
» FMA3, AVX512 instructions
» Virtualization
» Simultaneous multi-threading
» Frequency boost
» No integrated GPU
» Standard and high power
» 1-way processing
• Socket SP6

EPYC 9004 series[edit]

EPYC 9004 (Genoa/Genoa-X/Bergamo)
• Zen 4/4c microarchitecture
» 5 nm (0.005 micron)
» Server SoC
» Up to 128 cores
» Up to 4.1 GHz
» Up to 128 MB L2 cache
» Up to 384/1152 MB L3 cache
» 64-bit
» FMA3, AVX512 instructions
» Virtualization
» Simultaneous multi-threading
» Frequency boost
» No integrated GPU
» High to ultra high power
» Up to 2-way processing
• Socket SP5

EPYC Embedded 9004[edit]

EPYC 9004 (Genoa)
• Zen 4 microarchitecture
» 5 nm (0.005 micron)
» Embedded SoC
» Up to 96 cores
» Up to 3.25 GHz
» Up to 96 MB L2 cache
» Up to 384 MB L3 cache
» 64-bit
» FMA3, AVX512 instructions
» Virtualization
» Simultaneous multi-threading
» Frequency boost
» No integrated GPU
» High to ultra high power
» Up to 2-way processing
• Socket SP5

EPYC 9005 series[edit]

EPYC 9005 (Turin/Turin Dense)
• Zen 5/5c microarchitecture
» 3 nm/4 nm (0.003/0.004 micron)
» Server SoC
» Up to 96/192 cores
» Up to 4.2 GHz
» Up to 192 MB L2 cache
» Up to 512 MB L3 cache
» 64-bit
» FMA3, AVX512 instructions
» Virtualization
» Simultaneous multi-threading
» Frequency boost
» No integrated GPU
» High and ultra high power
» Up to 2-way processing
• Socket SP5

EPYC Embedded 9005[edit]

EPYC 9005 (Turin/Turin Dense)
• Zen 5/5c microarchitecture
» 3 nm/4 nm (0.003/0.004 micron)
» Embedded SoC
» Up to 192 cores
» Up to 3.65 GHz
» Up to 192 MB L2 cache
» Up to 512 MB L3 cache
» 64-bit
» FMA3, AVX512 instructions
» Virtualization
» Simultaneous multi-threading
» Frequency boost
» No integrated GPU
» High to ultra high power
» Up to 2-way processing
• Socket SP5

EPYC 9006 series[edit]

EPYC 9006 (Venice/Venice Dense)
• Zen 6/6c microarchitecture
» 2 nm/3 nm (0.002/0.003 micron)
» Server SoC
» Up to 96/256 cores
» Up to 4.2 GHz
» Up to 192 MB L2 cache
» Up to 512 MB L3 cache
» 64-bit
» FMA3, AVX512 instructions
» Virtualization
» Simultaneous multi-threading
» Frequency boost
» No integrated GPU
» High and ultra high power
» Up to 2-way processing
• Socket SP7
  • EPYC 9005 "Turin" (Zen 5): 96 Cores / 192 Threads / 16 CCDs
  • EPYC 9005 "Turin Dense" (Zen 5c): 192 Cores / 384 Threads / 12 CCDs
  • EPYC 9006 "Venice" (Zen 6): 96 Cores / 192 Threads / 8 CCDs
  • EPYC 9006 "Venice Dense" (Zen 6c): 256 Cores / 512 Threads / 8 CCDs

EPYC 4004 series[edit]

EPYC 4004 (Raphael-R)
• Zen 4 microarchitecture
» 5 nm (0.005 micron)
» Entry-level server SoC
» Up to 16 cores
» Up to 4.5 GHz
» Up to 16 MB L2 cache
» Up to 128 MB L3 cache
» 64-bit
» FMA3, AVX512 instructions
» Virtualization
» Simultaneous multi-threading
» Frequency boost
» Integrated graphics
» Medium to high power
» 1-way processing
• Socket AM5

EPYC 4005 series[edit]

EPYC 4005 (Grado)
• Zen 5 microarchitecture
» 3 nm (0.003 micron)
» Entry-level server SoC
» Up to 16 cores
» Up to 4.3 GHz
» Up to 16 MB L2 cache
» Up to 128 MB L3 cache
» 64-bit
» FMA3, AVX512 instructions
» Virtualization
» Simultaneous multi-threading
» Frequency boost
» Integrated graphics
» Medium and high power
» 1-way processing
• Socket AM5

EPYC 4006 series[edit]

EPYC 4006 (Weisshorn)
• Zen 6 microarchitecture
» 3 nm (0.003 micron)
» Entry-level server SoC
» Up to 16 cores
» Up to 4.3 GHz
» Up to 16 MB L2 cache
» Up to 128 MB L3 cache
» 64-bit
» FMA3, AVX512 instructions
» Virtualization
» Simultaneous multi-threading
» Frequency boost
» Integrated graphics
» Medium and high power
» 1-way processing
• Socket AM5
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