Revision as of 17:51, 18 October 2020

EPYC Embedded 3255 is a 64-bit octa-core x86 embedded microprocessor for dense servers and edge devices. Fabricated on a 14 nm process based on the Zen microarchitecture, this chip operates at 2.5 GHz with a TDP of 55 W and a turbo frequency of up to 3.1 GHz. This model supports a configurable TDP-down of 30 W and is distinguished from other EPYC Embedded 3000 Series processors by an industrial temperature range of -40 to 105 °C. The 3255 supports up to 512 GiB of dual-channel DDR4-2666 memory.

Cache

Main article: Zen § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 768 KiB 786,432 B 0.75 MiB L1I$ 512 KiB 524,288 B 0.5 MiB 8 × 64 KiB 4-way set associative   L1D$ 256 KiB 262,144 B 0.25 MiB 8 × 32 KiB 8-way set associative write-back L2$ 4 MiB 4,096 KiB 4,194,304 B 0.00391 GiB     8 × 512 KiB 8-way set associative write-back L3$ 16 MiB 16,384 KiB 16,777,216 B 0.0156 GiB     2 × 8 MiB

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR4-2666 Supports ECC Yes Max Mem 512 GiB Controllers 2 Channels 2 Max Bandwidth 39.74 GiB/s 40,693.76 MiB/s 42.671 GB/s 42,670.5 MB/s 0.0388 TiB/s 0.0427 TB/s Bandwidth Single 19.87 GiB/s Double 39.74 GiB/s

Expansions

The EPYC Embedded 3255 supports up to 32 PCIe Gen 3 (8 GT/s) lanes. Some of these lanes can be configured as SATA 3 (6 Gb/s) and 10 Gigabit Ethernet ports. Up to 8 SATA ports and 4 GbE ports are available on this model, as well as four USB 3.1 Gen 1 (5 Gb/s) ports, and the following low speed interfaces: EMMC, eSPI, GPIO, I2C, LPC, SMBus, SPI, UART.

[Edit/Modify Expansions Info]

	Expansion Options
PCIe Revision: 3.0 Max Lanes: 32 Configuration: x16, x8, x4, x2 USB Revision: 3.1 Max Ports: 4 SATA Revision: 3.0 Max Ports: 8

[Edit/Modify Network Info]

	Networking
	Ethernet 10GbE Yes (Ports: 4)

Features

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX MMX Extension EMMX Extended MMX Extension SSE Streaming SIMD Extensions SSE2 Streaming SIMD Extensions 2 SSE3 Streaming SIMD Extensions 3 SSSE3 Supplemental SSE3 SSE4.1 Streaming SIMD Extensions 4.1 SSE4.2 Streaming SIMD Extensions 4.2 SSE4a Streaming SIMD Extensions 4a AVX Advanced Vector Extensions AVX2 Advanced Vector Extensions 2 ABM Advanced Bit Manipulation BMI1 Bit Manipulation Instruction Set 1 BMI2 Bit Manipulation Instruction Set 2 FMA3 3-Operand Fused-Multiply-Add AES AES Encryption Instructions RdRand Hardware RNG SHA SHA Extensions ADX Multi-Precision Add-Carry CLMUL Carry-less Multiplication Extension F16C 16-bit Floating Point Conversion x86-16 16-bit x86 x86-32 32-bit x86 x86-64 64-bit x86 Real Real Mode Protected Protected Mode SMM System Management Mode FPU Integrated x87 FPU NX No-eXecute SMT Simultaneous Multithreading AMD-Vi AMD-Vi (I/O MMU virtualization) AMD-V AMD Virtualization SME Secure Memory Encryption TSME Transparent SME SEV Secure Encrypted Virtualization SenseMI SenseMI Technology

References

• "AMD EPYC™ Embedded 3000 Family", AMD Publ. #1887102, Rev. E, 2019
• "Embedded Processor Specifications". AMD.com. Retrieved October 2020.