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Difference between revisions of "cavium/microarchitectures/vulcan"
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(Key changes from {{broadcom|XLP II|l=arch}})
(Key changes from {{broadcom|XLP II|l=arch}})
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**** Roughly 10-20% more µOPs
 
**** Roughly 10-20% more µOPs
 
** New loop buffer
 
** New loop buffer
** New scheduler
+
** Execution Engine
*** Unified schedule (from distributed)
+
*** New scheduler
**** 60 entries
+
**** Unified schedule (from distributed)
** Large ROB (180 entries, up from 128)
+
***** 60 entries
 +
*** Large ROB (180 entries, up from 128)
 +
*** Execution Units
 +
**** New FP Unit (2, up from 1)
 +
**** Wider FP Units (128-bit, up from 64-bit)
 +
** Memory Subsystem
 +
*** Double load bandwidth (128-bit, up from 64-bit)
 +
*** New Store Data Unit
 +
*** Half L2 Cache Size (256 KiB, down form 512 KiB)
 
* Memory Controller
 
* Memory Controller
 
** DDR3 '''→''' DDR4
 
** DDR3 '''→''' DDR4

Revision as of 19:13, 28 May 2018

Edit Values
Vulcan µarch
General Info
Arch TypeCPU
DesignerBroadcomm, Cavium
ManufacturerTSMC
Introduction2018
Process16 nm
Core Configs16, 20, 24, 28, 30, 32
Pipeline
TypeSuperscalar, Superpipeline
OoOEYes
SpeculativeYes
Reg RenamingYes
Stages13-15
Decode4-way
Instructions
ISAARMv8.1
ExtensionsNEON
Cache
L1I Cache32 KiB/core
8-way set associative
L1D Cache32 KiB/core
8-way set associative
L2 Cache256 KiB/core
8-way set associative
L3 Cache1 MiB/core
Succession

Vulcan is a 16 nm high-performance 64-bit ARM microarchitecture designed by Broadcom and later Cavium for the server market.

Introduced in 2018, Vulcan-based microprocessors are branded as part of the ThunderX2 family.

History

Vulcan can trace its roots all the way back to Raza Microelectronics XLR family of MIPS processors from 2006. With the introduction of their XLR family in 2009, Raza (and later NetLogic) moved to a high-performance superscalar design with fine-grained 4-way multithreading support. In 2011, Broadcom acquired NetLogic Microsystems and integrated them Broadcom's Embedded Processor Group.

In 2013, Broadcom announced that they have licensed the ARMv7 and ARMv8 architectures, allowing them to develop their own microarchitectures based on the ISA. Vulcan is the outcome of this effort which involved adopting the ARM ISA instead of MIPS and enhancing the cores in various ways.

Architecture

Vulcan builds on the prior MIPS-based XLP II microarchitecture. The design has been substantially improved and changed to execute ARM (based on the ARMv8.1 ISA).

Key changes from XLP II

  • Converted to ARM ISA (from MIPS)
    • Aarch64, Aarch32
  • 16nm FinFET process (from 28 nm planar)
  • 40% IPC improvement
  • 25% higher clock (2.5 GHz, up from 2 GHz)
  • Core
    • Longer pipeline (15 stages, up from 13)
    • Double fetch throughput (4, up from 2)
    • New Decoder
      • Decodes ARMv8.1 (Instead of MIPS64 R5)
      • Decodes to micro-ops
        • Roughly 10-20% more µOPs
    • New loop buffer
    • Execution Engine
      • New scheduler
        • Unified schedule (from distributed)
          • 60 entries
      • Large ROB (180 entries, up from 128)
      • Execution Units
        • New FP Unit (2, up from 1)
        • Wider FP Units (128-bit, up from 64-bit)
    • Memory Subsystem
      • Double load bandwidth (128-bit, up from 64-bit)
      • New Store Data Unit
      • Half L2 Cache Size (256 KiB, down form 512 KiB)
  • Memory Controller
    • DDR3 DDR4
    • 4 8 channels
    • 1600 MT/s 2666 MT/s
    • 47.68 GiB/s 158.9 GiB/s

Block Diagram

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Memory Hierarchy

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Overview

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Core

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All Vulcan Chips

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References

  • Some information was obtained directly from Broadcom
  • Some information was obtained directly from Cavium

See also

codenameVulcan +
core count16 +, 20 +, 24 +, 28 +, 30 + and 32 +
designerBroadcomm + and Cavium +
first launched2018 +
full page namecavium/microarchitectures/vulcan +
instance ofmicroarchitecture +
instruction set architectureARMv8.1 +
manufacturerTSMC +
microarchitecture typeCPU +
nameVulcan +
pipeline stages (max)15 +
pipeline stages (min)13 +
process16 nm (0.016 μm, 1.6e-5 mm) +