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The last component of the System Agent and an entirely new addition in Skylake is the Image Processing Unit (IPU) which incorporates an [[image signal processor]] (ISP) on-die. The IPU is only available on mobile models and was added in order to improve and streamline (i.e. form factor and consistent set of features and quality) the implementation and performance of tablets and 2-in-1s. Previously this would require the assistance of an external component and the implementations varied by designer.
 
The last component of the System Agent and an entirely new addition in Skylake is the Image Processing Unit (IPU) which incorporates an [[image signal processor]] (ISP) on-die. The IPU is only available on mobile models and was added in order to improve and streamline (i.e. form factor and consistent set of features and quality) the implementation and performance of tablets and 2-in-1s. Previously this would require the assistance of an external component and the implementations varied by designer.
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== Core (Client) ==
 
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=== Overview ===
 
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Skylake shares most of the development vectors with its predecessor while introducing a one of new constraint. The overall goals were:
 
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* Performance improvements - the traditional way of milking more performance by increasing the instructions per cycle as well as clock frequency.
 
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* Power efficiency - reduction of power for all functional blocks
 
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* Security enhancements - new security features are implemented in hardware in the core
 
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* Configurability 
 
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==== Configurability ====
 
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[[File:skylake master core configs.svg|right|200px]]
 
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Intel has been experiencing a growing divergence in functionality over the last number of iterations of [[intel/microarchitectures|their microarchitecture]] between their mainstream consumer products and their high-end HPC/server models. Traditionally, Intel has been using the same exact core design for everything from their lowest end value models (e.g. {{intel|Celeron}}) all the way up to the highest-performance enterprise models (e.g. {{intel|Xeon E7}}). While the two have fundamentally different chip architectures, they use the same exact CPU core architecture as the building block.
 
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This design philosophy has changed with Skylake. In order to better accommodate the different functionalities of each segment without sacrificing features or making unnecessary compromises Intel went with a configurable core. The Skylake core is a single development project, making up a master superset core. The project result in two derivatives: one for servers and one for clients. All mainstream models (from {{intel|Celeron}}/{{intel|Pentium (2009)|Pentium}} all the way up to {{intel|Core i7}}/{{intel|Xeon E3}}) use the client core configuration. Server models (e.g. {{intel|Xeon E5}}/{{intel|Xeon E7}}) will be using the new server configuration.
 
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The server core is considerably larger than the client one, featuring [[Advanced Vector Extensions 512]] (AVX-512). Skylake servers support what was formerly called AVX3.2 (AVX512F + AVX512CD + AVX512BW + AVX512DQ + AVX512VL). Additionally, those processors Memory Protection Keys for Userspace (PKU), {{x86|PCOMMIT}}, and {{x86|CLWB}}.
 
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=== Pipeline ===
 
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The Skylake core focuses on extracting performance and reducing power through a number of key ways. Intel builds Skylake on previous microarchitectures, descendants of {{\\|Sandy Bridge}}. For the core to increase the overall performance, Intel focused on extracting additional [[instruction parallelism|parallelism]].
 
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==== Broad Overview ====
 
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At a 5,000 foot view, Skylake represents the logical evolution from {{\\|Haswell}} and {{\\|Broadwell}}. Therefore, despite some significant differences from the previous microarchitecture, the overall designs is fundamentally the same and can be seen as enhancements over Broadwell rather than a complete change.
 
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[[File:intel common arch post ucache.svg|left|250px]]
 
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The pipeline can be broken down into three areas: the front-end, back-end or execution engine, and the memory subsystem. The goal of the [[front-end]] is to feed the back-end with a sufficient stream of operations which it gets by [[decoding instructions]] coming from memory. The front-end has two major pathways: the [[µOPs cache]] path and the legacy path. The legacy path is the traditional path whereby variable-length [[x86]] instructions are fetched from the [[level 1 instruction cache]], queued, and consequently get decoded into simpler, fixed-length [[µOPs]]. The alternative and much more desired path is the µOPs cache path whereby a [[cache]] containing already decoded µOPs receives a hit allowing the µOPs to be sent directly to the decode queue.
 
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Regardless of which path an instruction ends up taking it will eventually arrive at the decode queue. The IDQ represents the end of the front-end and the [[in-order]] part of the machine and the start of the execution engine which operates [[out-of-order]].
 
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In the back-end, the micro-operations visit the [[reorder buffer]]. It's there where register allocation, renaming, and [[instruction retired|retiring]] takes place. At this stage a number of other optimizations are also done. From the reorder buffer, µOPs are sent to the unified scheduler. The scheduler has a number of exit ports, each wired to a set of different execution units. Some units can perform basic ALU operations, others can do multiplication and division, with some units capable of more complex operations such as various vector operations. The scheduler is effectively in charge of queuing the µOPs on the appropriate port so they can be executed by the appropriate unit.
 
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Some µOPs deal with memory access (e.g. [[instruction load|load]] & [[instruction store|store]]). Those will be sent on dedicated scheduler ports that can perform those memory operations. Store operations go to the store buffer which is also capable of performing forwarding when needed. Likewise, Load operations come from the load buffer. Skylake features a dedicated 32 KiB level 1 data cache and a dedicated 32 KiB level 1 instruction cache. It also features a core-private 256 KiB L2 cache that is shared by both of the L1 caches.
 
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Each core enjoys a slice of a third level of cache that is shared by all the core. In the client configuration for Skylake, there are either [[two cores]] or [[four cores]] connected while in the server configuration, up to [[28 cores]] may be hooked together on a single chip.
 
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{{clear}}
 
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==== Front-end ====
 
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The front-end is is tasked with the challenge of fetching the complex [[x86]] instructions from memory, decoding them, and delivering them to the execution units. In other words, the front end needs to be able to consistently deliver enough [[µOPs]] from the instruction code stream to keep the back-end busy. When the back-end is not being fully utilized, the core is not reaching its full performance. A poorly or under-performing front-end will translate directly to a poorly performing core. This challenge is further complicated by various redirection such as branches and the complex nature of the [[x86]] instructions themselves.
 
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===== Fetch & pre-decoding =====
 
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On their first pass, instructions should have already been prefetched from the [[L2 cache]] and into the [[L1 cache]]. The L1 is a 32 [[KiB]], 8-way set associative cache, identical in size and organization to {{intel|microarchitectures|previous generations}}. Skylake fetching is done on a 16-byte fetch window. A window size that has not changed in a number of generations. Up to 16 bytes of code can be fetched each cycle. Note that fetcher is shared evenly between two thread, so that each thread gets every other cycle. At this point they are still [[macro-ops]] (i.e. variable-length [[x86]] architectural instruction). Instructions are brought into the pre-decode buffer for initial preparation.
 
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[[File:skylake fetch.svg|left|300px]]
 
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[[x86]] instructions are complex, variable length, have inconsistent encoding, and may contain multiple operations. At the pre-decode buffer the instructions boundaries get detected and marked. This is a fairly difficult task because each instruction can vary from a single byte all the way up to fifteen. Moreover, determining the length requires inspecting a couple of bytes of the instruction. In addition boundary marking, prefixes are also decoded and checked for various properties such as branches. As with previous microarchitectures, the pre-decoder has a [[throughput]] of 6 [[macro-ops]] per cycle or until all 16 bytes are consumed, whichever happens first. Note that the predecoder will not load a new 16-byte block until the previous block has been fully exhausted. For example, suppose a new chunk was loaded, resulting in 7 instructions. In the first cycle, 6 instructions will be processed and a whole second cycle will be wasted for that last instruction. This will produce the much lower throughput of 3.5 instructions per cycle which is considerably less than optimal. Likewise, if the 16-byte block resulted in just 4 instructions with 1 byte of the 5th instruction received, the first 4 instructions will be processed in the first cycle and a second cycle will be required for the last instruction. This will produce an average throughput of 2.5 instructions per cycle. Note that there is a special case for {{x86|length-changing prefix}} (LCPs) which will incur additional pre-decoding costs. Real code is often less than 4 bytes which usually results in a good rate.
 
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All of this works along with the branch prediction unit which attempts to guess the flow of instructions. In Skylake, the [[branch predictor]] has also been improved. The branch predictor now has reduced penalty (i.e. lower latency) for wrong direct jump target prediction. Additionally, the predictor in Skylake can inspect further in the byte stream than in previous architectures. The intimate improvements done in the branch predictor were not further disclosed by Intel.
 
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====== Instruction Queue & MOP-Fusion ======
 
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{| style="border: 1px solid gray; float: right; margin: 10px; padding: 5px"
 
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| [[MOP-Fusion]] Example:
 
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|-
 
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|
 
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<pre>cmp eax, [mem]
 
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jne loop</pre>
 
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| '''→'''
 
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| <pre>cmpjne eax, [mem], loop</pre>
 
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|}
 
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{{see also|Macro-Operation Fusion}}
 
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The pre-decoded instructions are delivered to the Instruction Queue (IQ). In {{\\|Broadwell}}, the Instruction Queue has been increased to 25 entries duplicated over for each thread (i.e. 50 total entries). It's unclear if that has changed with Skylake. One key optimization the instruction queue does is [[macro-op fusion]]. Skylake can fuse two [[macro-ops]] into a single complex one in a number of cases. In cases where a {{x86|test}} or {{x86|compare}} instruction with a subsequent conditional jump is detected, it will be converted into a single compare-and-branch instruction. Those fused instructions remain fused throughout the entire pipeline and get executed as a single operation by the branch unit thereby saving bandwidth everywhere. Only one such fusion can be performed each cycle.
 
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===== Decoding =====
 
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[[File:skylake decode.svg|right|425px]]
 
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Up to five pre-decoded instructions are sent to the decoders each cycle. Like the fetchers, the Decoders alternate between the two thread each cycle. Decoders read in [[macro-operations]] and emit regular, fixed length [[µOPs]]. Skylake represents a big genealogical change from the last couple of microarchitectures. Skylake's pipeline is wider than it predecessors; Skylake adds another [[simple decoder]]. The five decoders are asymmetric; the first one, Decoder 0,  is a [[complex decoder]] while the other four are [[simple decoders]]. A simple decoder is capable of translating instructions that emit a single fused-[[µOP]]. By contrast, a [[complex decoder]] can decode anywhere from one to four fused-µOPs. Skylake is now capable of decoding 5 macro-ops per cycle or 25% more than {{\\|Broadwell}}, however this does not translates directly to direct IPC uplift to due to various other more restricting points in the pipeline. Intel chose not increase the number of complex decoders because it's much harder to extract additional parallelism from the µOPs emitted by a complex instruction. Overall up to 5 simple instructions can be decoded each cycle with lesser amounts if the complex decoder needs to emit addition µOPs; i.e., for each additional µOP the complex decoder needs to emit, 1 less simple decoder can operate. In other words, for each additional µOP the complex decoder emits, one less decoder is active.
 
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====== MSROM & Stack Engine ======
 
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There are more complex instructions that are not trivial to be decoded even by complex decoder. For instructions that transform into more than four µOPs, the instruction detours through the [[microcode sequencer]] (MS) ROM. When that happens, up to 4 µOPs/cycle are emitted until the microcode sequencer is done. During that time, the decoders are disabled.
 
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[[x86]] has dedicated [[stack machine]] operations. Instructions such as <code>{{x86|PUSH}}</code>, <code>{{x86|POP}}</code>, as well as <code>{{x86|CALL}}</code>, and <code>{{x86|RET}}</code> all operate on the [[stack pointer]] (<code>{{x86|ESP}}</code>). Without any specialized hardware, such operations would would need to be sent to the back-end for execution using the general purpose ALUs, using up some of the bandwidth and utilizing scheduler and execution units resources. Since {{\\|Pentium M}}, Intel has been making use of a [[Stack Engine]]. The Stack Engine has a set of three dedicated adders it uses to perform and eliminate the stack-updating µOPs (i.e. capable of handling three additions per cycle). Instruction such as <code>{{x86|PUSH}}</code> are translated into a store and a subtraction of 4 from <code>{{x86|ESP}}</code>. The subtraction in this case will be done by the Stack Engine. The Stack Engine sits after the [[instruction decode|decoders]] and monitors the µOPs stream as it passes by. Incoming stack-modifying operations are caught by the Stack Engine. This operation alleviate the burden of the pipeline from stack pointer-modifying µOPs. In other words, it's cheaper and faster to calculate stack pointer targets at the Stack Engine than it is to send those operations down the pipeline to be done by the execution units (i.e., general purpose ALUs).
 
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===== µOP cache & x86 tax =====
 
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[[File:skylake ucache.svg|right|400px]]
 
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Decoding the variable-length, inconsistent, and complex [[x86]] instructions is a nontrivial task. It's also expensive in terms of performance and power. Therefore, the best way for the pipeline to avoid those things is to simply not decode the instructions. This is the job of the [[µOP cache]] or the Decoded Stream Buffer (DSB). Skylake's µOP cache is organized similarly to previous generations like {{\\|Sandy Bridge}}, however both the bandwidth and the tracking window was increased. The cache is organized into 32 sets of 8 cache lines with each line holding up to 6 µOP for a total of 1,536 µOPs. Whereas previously (e.g. {{\\|Haswell}}) the µOP cache operated on 32-byte windows, in Skylake the window size has been doubled to 64-bytes. The micro-operation cache is competitively shared between the two threads and can also hold pointers to the microcode. The µOP cache has an average hit rate of 80%.
 
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A hit in the µOP allows for up to 6 µOP (i.e., entire line) per cycle to be sent directly to the Instruction Decode Queue (IDQ), bypassing all the pre-decoding and decoding that would otherwise have to be done. Whereas the legacy decode path works in 16-byte instruction fetch windows, the µOP cache has no such restriction and can deliver 6 µOP/cycle corresponding to the much bigger 64-byte window. Previously (e.g., {{\\|Broadwell}}), the bandwidth was lower at 4 µOP per cycle. The 1.5x bandwidth increase greatly improves the numbers of µOP that the back-end can take advantage of in the [[out-of-order]] part of the machine.
 
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===== Allocation Queue =====
 
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The emitted µOPs from the decoders are sent directly to the Allocation Queue (AQ) or Instruction Decode Queue (IDQ). The Allocation Queue acts as the interface between the front-end ([[in-order]]) and the back-end ([[out-of-order]]). Skylake's Allocation Queue has more than doubled from {{\\|Broadwell}} from 28-entries per thread to 64-entries per thread. Unlike in {{\\|Haswell}}, the IDQ is no longer competitively shared; it's partitioned between two active threads. The queue's purpose is effectively help absorb [[bubbles]] which may be introduced in the front-end, ensuring that a steady stream of 6 µOPs are delivered each cycle.
 
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====== µOP-Fusion & LSD ======
 
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The IDQ does a number of additional optimizations as it queues instructions. The Loop Stream Detector (LSD) is a mechanism inside the IDQ capable of detecting loops that fit in the IDQ and lock them down. That is, the LSD can stream the same sequence of µOPs directly from the IDQ continuously without any additional [[instruction fetch|fetching]], [[instruction decode|decoding]], or utilizing additional caches or resources. Streaming continues indefinitely until reaching a branch [[mis-prediction]]. Note that while the LSD is active, the rest of the front-end is effectively disabled.
 
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The LSD in Skylake can take advantage of the considerably larger IDQ; capable of detecting loops up to 64 µOPs per thread. The LSD is particularly excellent in for many common algorithms that are found in many programs (e.g., tight loops, intensive calc loops, searches, etc..).
 
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* '''NOTE:''' A microcode update appear to have disabled the LSD on client processors. See [[#Front-end_2|§ Server Front-end]].
 
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==== Execution engine ====
 
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[[File:skylake rob.svg|right|450px]]
 
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Skylake's back-end or execution engine deals with the execution of [[out-of-order]] operations. Much of the design is inherited from previous architectures such as {{\\|Haswell}} but has been widened to explorer more [[instruction-level parallelism]] opportunities. From the allocation queue instructions are sent to the [[Reorder Buffer]] (ROB) at the rate of up to 6 fused-µOPs each cycle. Skylake's throughput is up by 2 fused-µOPs per cycle from {{\\|Broadwell}} in order to accommodate the wider front-end.
 
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===== Renaming & Allocation =====
 
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Like the front-end, the [[Reorder Buffer]] has been increased to 224 entries, 32 entries more than {{\\|Broadwell}}. It is at this stage that [[architectural registers]] are mapped onto the underlying [[physical registers]]. Other additional bookkeeping tasks are also done at this point such as allocating resources for stores, loads, and determining all possible scheduler ports. Register renaming is also controlled by the [[Register Alias Table]] (RAT) which is used to mark where the data we depend on is coming from (after that value, too, came from an instruction that has previously been renamed). In {{intel|microarchitectures|previous microarchitectures}}, the RAT could handle 4 µOPs each cycle. Intel has not disclosed if that has changed in Skylake but it's possible. If this has not change, Skylake can rename any four registers per cycle. This includes the same register renamed four times in a single cycle. If the rename has not increased in Skylake, some aspects of improvements that were done in the prefetch/decode stages are effectively lost. Note that the ROB still operates on fused µOPs, therefore 4 µOPs can effectively be as high as 8 µOPs.
 
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It should be noted that there is no special costs involved in splitting up fused µOPs before execution or [[retirement]] and the two fused µOPs only occupy a single entry in the ROB.
 
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Since Skylake performs [[speculative execution]], it can speculate incorrectly. When this happens, the architectural state is invalidated and as such needs to be rolled back to the last known valid state. Skylake has a 48-entry [[Branch Order Buffer]] (BOB) that keeps tracks of those states for this very purpose.
 
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===== Optimizations =====
 
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Skylake as a number of optimizations it performs prior to entering the out-of-order and renaming part. Three of those optimizations include [[Move Elimination]] and [[Zeroing Idioms]], and [[Ones Idioms]]. A Move Elimination is capable of eliminating register-to-register moves (including chained moves) prior to bookkeeping at the ROB, allowing those µOPs to save resources and eliminating them entirely. Eliminated moves are zero latency and are entirely removed from the pipeline. This optimization does not always succeed; when it fails, the operands were simply not ready. On average this optimization is almost always successful (upward of 85% in most cases). Move elimination works on all 32- and 64-bit GP integer registers as well as all 128- and 256-bit vector registers.
 
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{| style="border: 1px solid gray; float: right; margin: 10px; padding: 5px; width: 350px;"
 
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| [[Zeroing Idiom]] Example:
 
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|-
 
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| <pre>xor eax, eax</pre>
 
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|-
 
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| Not only does this instruction get eliminated at the ROB, but it's actually encoded as just 2 bytes <code>31 C0</code> vs the 4 bytes for <code>{{x86|mov}} {{x86|eax}}, 0x0</code> which is encoded as <code>b8 00 00 00 00</code>.
 
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|}
 
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There are some exceptions that Skylake will not optimize, most dealing with [[signedness]]. [[sign extension|sign-extended]] moves cannot be eliminated and neither can zero-extended from 16-bit to 32/64 big registers (note that 8-bit to 32/64 works). Likewise, in the other direction, no moves to 8/16-bit registers can be eliminated. A move of a register to itself is never eliminated.
 
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When instructions use registers that are independent of their prior values, another optimization opportunity can be exploited. A second common optimization performed in Skylake around the same time is [[Zeroing Idioms]] elimination. A number common zeroing idioms are recognized and consequently eliminated in much the same way as the move eliminations are performed. Skylake recognizes instructions such as <code>{{x86|XOR}}</code>, <code>{{x86|PXOR}}</code>, and <code>{{x86|XORPS}}</code> as zeroing idioms when the [[source operand|source]] and [[destination operand|destination]] operands are the same. Those optimizations are done at the same rate as renaming during renaming (at 4 µOPs per cycle) and the register is simply set to zero.
 
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The [[ones idioms]] is another dependency breaking idiom that can be optimized. In all the various {{x86|PCMPEQ|PCMPEQx}} instructions that perform packed comparison the same register with itself always set all bits to one. On those cases, while the µOP still has to be executed, the instructions may be scheduled as soon as possible because all the decencies are resolved.
 
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===== Scheduler =====
 
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[[File:skylake scheduler.svg|right|500px]]
 
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The scheduler itself was increased by 50%; with up to 97 entries (from 64 in {{\\|Broadwell}}) being competitively shared between the two threads. Skylake continues with a unified design; this is in contrast to designs such as [[AMD]]'s {{amd|Zen|l=arch}} which uses a split design each one holding different types of µOPs. Scheduler includes the two register files for integers and vectors. It's in those [[register files]] that output operand data is store. In Skylake, the [[integer]] [[register file]] was also slightly increased from 160 entries to 180.
 
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At this point µOPs are not longer fused and will be dispatched to the execution units independently. The scheduler holds the µOPs while they wait to be executed. A µOP could be waiting on an operand that has not arrived (e.g., fetched from memory or currently being calculated from another µOPs) or because the execution unit it needs is busy. Once the µOP is ready, they are dispatched through their designated port. The scheduler will send the oldest ready µOP to be executed on each of the eight ports each cycle.
 
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The scheduler had its ports rearranged to better balance various instructions. For example, divide and [[sqrt]] instructions latency and throughput were improved. The latency and throughput of [[floating point]] ADD, MUL, and FMA were made uniformed at 4 cycles with a throughput of 2 µOPs/clock. Likewise the latency of {{x86|AES|AES instructions}} were significantly reduced from 7 cycles down to 4.
 
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====== Scheduler Ports & Execution Units ======
 
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<table class="wikitable">
 
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<tr><th colspan="2">Scheduler Ports Designation</th></tr>
 
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<tr><th rowspan="5">Port 0</th><td>Integer/Vector Arithmetic, Multiplication, Logic, Shift, and String ops</td></tr>
 
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<tr><td>[[FP]] Add, [[Multiply]], [[FMA]]</td></tr>
 
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<tr><td>Integer/FP Division and [[Square Root]]</td></tr>
 
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<tr><td>[[AES]] Encryption</td></tr>
 
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<tr><td>Branch2</td></tr>
 
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<tr><th rowspan="2">Port 1</th><td>Integer/Vector Arithmetic, Multiplication, Logic, Shift, and Bit Scanning</td></tr>
 
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<tr><td>[[FP]] Add, [[Multiply]], [[FMA]]</td></tr>
 
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<tr><th rowspan="3">Port 5</th><td>Integer/Vector Arithmetic, Logic</td></tr>
 
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<tr><td>Vector Permute</td></tr>
 
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<tr><td>[[x87]] FP Add, Composite Int, CLMUL</td></tr>
 
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<tr><th rowspan="2">Port 6</th><td>Integer Arithmetic, Logic, Shift</td></tr>
 
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<tr><td>Branch</td></tr>
 
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<tr><th>Port 2</th><td>Load, AGU</td></tr>
 
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<tr><th>Port 3</th><td>Load, AGU</td></tr>
 
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<tr><th>Port 4</th><td>Store, AGU</td></tr>
 
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<tr><th>Port 7</th><td>AGU</td></tr>
 
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</table>
 
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{| class="wikitable collapsible collapsed"
 
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|-
 
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! colspan="3" | Execution Units
 
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|-
 
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! Execution Unit !! # of Units !! Instructions
 
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|-
 
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| ALU || 4 || add, and, cmp, or, test, xor, movzx, movsx, mov, (v)movdqu, (v)movdqa, (v)movap*, (v)movup*
 
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|-
 
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| DIV || 1 || divp*, divs*, vdiv*, sqrt*, vsqrt*, rcp*, vrcp*, rsqrt*, idiv
 
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|-
 
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| Shift || 2 || sal, shl, rol, adc, sarx, adcx, adox, etc...
 
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|-
 
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| Shuffle || 1 || (v)shufp*, vperm*, (v)pack*, (v)unpck*, (v)punpck*, (v)pshuf*, (v)pslldq, (v)alignr, (v)pmovzx*, vbroadcast*, (v)pslldq, (v)psrldq, (v)pblendw
 
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|-
 
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| Slow Int || 1 || mul, imul, bsr, rcl, shld, mulx, pdep, etc...
 
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|-
 
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| Bit Manipulation || 2 || andn, bextr, blsi, blsmsk, bzhi, etc
 
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|-
 
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| FP Mov || 1 || (v)movsd/ss, (v)movd gpr
 
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|-
 
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| SIMD Misc || 1 || STTNI, (v)pclmulqdq, (v)psadw, vector shift count in xmm
 
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|-
 
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| Vec ALU || 3 || (v)pand, (v)por, (v)pxor, (v)movq, (v)movq, (v)movap*, (v)movup*, (v)andp*, (v)orp*, (v)paddb/w/d/q, (v)blendv*, (v)blendp*, (v)pblendd
 
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|-
 
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| Vec Shift || 2 || (v)psllv*, (v)psrlv*, vector shift count in imm8
 
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|-
 
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| Vec Add || 2 || (v)addp*, (v)cmpp*, (v)max*, (v)min*, (v)padds*, (v)paddus*, (v)psign, (v)pabs, (v)pavgb, (v)pcmpeq*, (v)pmax, (v)cvtps2dq, (v)cvtdq2ps, (v)cvtsd2si, (v)cvtss2si
 
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|-
 
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| Vec Mul || 2 || (v)mul*, (v)pmul*, (v)pmadd*
 
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|-
 
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|colspan="3" | This table was taken verbatim from the Intel manual. Execution unit mapping to {{x86|MMX|MMX instructions}} are not included.
 
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|}
 
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===== Retirement =====
 
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Once a µOP executes, or in the case of fused µOPs both µOPs have executed, they can be [[retired]]. {{\\|Haswell}} is able to commit up to four fused µOPs each cycle per thread. Retirement happens [[in-order]] and releases any used resources such as those used to keep track in the [[reorder buffer]]. Because the allocation queue delivery in Skylake has been increased to 6 µOPs (12 unfused) from previously 4 µOPs (8 unfused) per cycle, the [[SMT]] implementation in Skylake should have some additional efficiency as there's now better chance for higher sustainable retirement rate.
 
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==== Memory subsystem ====
 
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[[File:skylake mem subsystem.svg|right|300px]]
 
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Skylake's memory subsystem is in charge of the loads and store requests and ordering. Since {{\\|Haswell}}, it's possible to sustain two memory reads (on ports 2 and 3) and one memory write (on port 4) each cycle. Each memory operation can be of any register size up to 256 bits. Skylake memory subsystem has been improved. The store buffer has been increased by 14 entries from {{\\|Broadwell}} to 56 for a total of 128 simultaneous memory operations in-flight or roughly 60% of all µOPs. Special care was taken to reduce the penalty for page-split loads; previously scenarios involving page-split loads were thought to be rarer than they actually are. This was addressed in Skylake with page-split loads are now made equal to other splits loads. Expect page split load penalty down to 5 cycles from 100 cycles in {{\\|Broadwell}}. The average latency to forward a load to store has also been improved and stores that miss in the L1$ generate L2$ requests to the next level cache much earlier in Skylake than before.
 
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The L2 to L1 bandwidth in Skylake is the same as {{\\|Haswell}} at 64 bytes per cycle in either direction. Note that one operation can be done each cycle; i.e., the L1 can either receive data from the L1 or send data to the Load/Store buffers each cycle, but not both. Latency from L2$ to L3$ has also been increased from 4 cycles/line to 2 cycles/line. The bandwidth from the level 2 cache to the shared level 3 is 32 bytes per cycle.
 
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=== eDRAM architectural changes ===
 
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Intel ships a number of products with [[Embedded DRAM]] incorporated on package in order to increase performance of the [[integrated graphics]] and to a lesser degree the code through additional bandwidth and caching. There has been a number of significant architectural changes in how the [[eDRAM]] works in Skylake.
 
−
 
−
In {{\\|Broadwell}}, the [[eDRAM]] was statically attached to the [[last level cache|LLC]] (last level cache, L3$ from the perspective of the [[CPU Cores]] and L4$ from the perspective of the [[IGP]]), effectively stealing half a [[Mebibyte]] per core in the process, but behaving as an architectural true level 4 cache. This was fundamentally changed in Skylake. In Skylake, Intel removed the [[eDRAM]] from the LLC to its own array, re-freeing the 512 KiB (hence the 1.5 MiB/core in Broadwell and 2 MiB back in Skylake), but also removing the undesired dependency between the capacity of the eDRAM and the number of cores. Skylake's cache is effectively no longer a true level 4 cache but rather a memory side cache. This has a number of benefits such as that each and every memory access that goes through the [[memory controller]] gets looked up in the eDRAM. On a satisfied hit, the value is obtained from there. On a miss, a value gets allocated and stored in the eDRAM (subject to a number of restrictions, for example no I/O devices requests get cached on the eDRAM).
 
−
 
−
{| class="wikitable" style="margin: auto;"
 
−
! colspan="2" | Skylake vs Broadwell eDRAM Architecture
 
−
|-
 
−
! Broadwell !! Skylake
 
−
|-
 
−
| [[File:broadwell edram setup.svg|350px]] || [[File:skylake edram setup.svg|350px]]
 
−
|}
 
−
 
−
The new eDRAM changes mean it's no longer architectural - capable of caching any data (including "unreachable memory", display engines, and effectively any memory transfer not bound by software restrictions) and is entirely invisible to software (one exception noted later) in terms of coherency (note that no flushing is thus necessary to maintain coherency), ordering, or other organizational details. For optimal graphics performance, the graphics driver may decide to limit certain memory accesses to only the eDRAM, only the LLC, or in both of them.
 
  
 
== Overview (Server) ==
 
== Overview (Server) ==
Line 725: Line 532:
  
 
Skylake processors are designed for scalability, supporting 2-way, 4-way, and 8-way multiprocessing through Intel's new {{intel|Ultra Path Interconnect}} (UPI) interconnect links, with two to three links being offered (see [[#Scalability|§ Scalability]]). High-end models have node controller support allowing higher way (e.g., 32-way multiprocessing).
 
Skylake processors are designed for scalability, supporting 2-way, 4-way, and 8-way multiprocessing through Intel's new {{intel|Ultra Path Interconnect}} (UPI) interconnect links, with two to three links being offered (see [[#Scalability|§ Scalability]]). High-end models have node controller support allowing higher way (e.g., 32-way multiprocessing).
−
 
−
== Server Architecture ==
 
−
There are a number of major differences in the Skylake server configuration vs the client configuration.
 
−
=== Pipeline ===
 
−
All the changes and improvements done to the client pipeline is also found in the server configuration.
 
−
==== Front-end ====
 
−
Other than the large amount of changes described in [[#Front-end|client front-end]], there are no server-specific changes that were done to the front-end with the exception of the LSD. The Loop Stream Detector (LSD) has been disabled. While the exact reason is not known, it might be related to a severe issue that [https://lists.debian.org/debian-devel/2017/06/msg00308.html was experienced by] the OCaml Development Team. The issue [https://lists.debian.org/debian-devel/2017/06/msg00308.html was patched via microcode] on the client platform, however this change might indicate it was possibly disabled on there as well. The exact implications of this are unknown.
 
−
 
−
==== Execution engine ====
 
−
[[File:skylake scheduler server.svg|right|500px]]
 
−
This is the first implementation to incorporate {{x86|AVX-512}}, a 512-bit [[SIMD]] [[x86]] instruction set extension. Intel introduced AVX-512 in two different ways:
 
−
 
−
In the simple implementation, the variants used in the {{intel|Xeon Bronze|entry-level}} and {{intel|Xeon Silver|mid-range}} Xeon servers, AVX-512 fuses Port 0 and Port 1 to form a 512-bit unit. Since those two ports are 256-wide, an AVX-512 option that is dispatched by the scheduler to port 0 will execute on both ports. Note that unrelated operations can still execute in parallel. For example, an AVX-512 operation and an Int ALU operation may execute in parallel - the AVX-512 is dispatched on port 0 and use the AVX unit on port 1 as well and the Int ALU operation will execute independently in parallel on port 1.
 
−
 
−
In the {{intel|Xeon Gold|high-end}} and {{intel|Xeon Platinum|highest}} performance Xeons, Intel added a second dedicated AVX-512 unit in addition to the fused Port0-1 operations described above. The dedicated unit is situated on Port 5.
 
−
 
−
==== Implementation ====
 
−
Physically, Intel added 768 KiB L2 cache and the second AVX-512 VPU externally to the core.
 
−
 
−
[[File:skylake sp added cach and vpu.png|left|300px]]
 
−
 
−
==== Memory subsystem ====
 
−
[[File:skylake-sp memory.svg|right|300px]]
 
−
The [[medium level cache]] (MLC) and [[last level cache]] (LLC) was rebalanced. Traditionally, Intel had a 256 KiB [[L2 cache]] which was duplicated along with the L1s over in the LLC which was 2.5 MiB. That is, prior to Skylake, the 256 KiB L2 cache actually took up 512 KiB of space for a total of 2.25 mebibytes effective cache per core. In Skylake Intel doubled the L2 and quadrupled the effective capacity to 1 MiB while decreasing the LLC to 1.375 MiB. The LLC is also now made [[non-inclusive cache|non-inclusive]], i.e., the L2 may or may not be in the L3 (no guarantee is made); what stored where will depend on the particular access pattern of the executing application, the size of code and data accessed, and the inter-core sharing behavior.
 
−
<!--
 
−
[[File:skylake server cache bandwidth.svg|left|200px]]-->
 
−
Having an inclusive L3 makes cache coherence considerably easier to implement. [[Snooping]] only requires checking the L3 cache tags to know if the data is on board and in which core. It also makes passing data around a bit more efficient. It's currently unknown what mechanism is being used to reduce snooping. In the past, Intel has discussed a couple of additional options they were researching such as NCID (non-inclusive cache, inclusive directory architecture). It's possible that a NCID is being used in Skylake or a related derivative. These changes also mean that software optimized for data placing in the various caches needs to be revised for the new changes, particularly in situations where data is not shared, the overall capacity can be treated as L2+L3 for a total of 2.375 MiB.
 
−
 
−
<!-- THIS NEEDS DOUBLE CHECKING, INTEL's INFO IS VERY UNCLEAR
 
−
With an increase to the L2 which is now 1 MiB, there is a latency penalty of 2 additional cycles (to 14 cycles from 12) but the max bandwidth from the L3 has also doubled accordingly to 64 bytes/cycle (from 32 B/cycle) with a sustainable bandwidth of 52 B/cycle. The L2 cache line size is 64 B and is 16-way set associative.
 
−
-->
 
−
{{clear}}
 
−
 
−
=== Mesh Architecture ===
 
−
[[File:skylake sp xcc die config.png|right|400px]]
 
−
On the {{intel|microarchitectures|previous number of generations}}, Intel has been adding cores onto the die and connecting them via a {{intel|ring architecture}}. This was sufficient until recently. With each generation, the added cores increased the access latency while lowering the available bandwidth per core. Intel mitigated this problem by splitting up the die into two halves each on its own ring. This reduced hopping distance and added additional bandwidth but it did not solve the growing fundamental inefficiencies of the ring architecture.
 
−
 
−
This was completely addressed with the new mesh architecture that is implemented in the Skylake server processors. The mesh is arranged as a matrix of vertical and horizontal communication paths which allow communication to take the shortest path to the correct node. The new mesh architecture implements a modular design for the routing resources in order to remove the various bottlenecks. That is, the mesh architecture now integrates the caching agent, the home agent, and the IO subsystem on the mesh interconnect distributed across all the cores. Each core now has its own associated LLC slice as well as the snooping filter and the Caching and Home Agent (CHA). Additional nodes such as the two memory controllers, the {{intel|Ultra Path Interconnect}} (UPI) nodes and PCIe are not independent node on the mesh as well and they now behave identically to any other node/core in the network. This means that in addition to the performance increase expected from core-to-core and core-to-memory latency, there should be substantial increase in I/O performance. The CHA which is found on each of the LLC slices now maps addresses being accessed to the specific LLC bank, memory controller, or I/O subsystem. This provides the necessary information required for the routing to take place.
 
−
 
−
==== Cache Coherency ====
 
−
Given the new mesh architecture, new tradeoffs were involved.  The new {{intel|UPI}} inter-socket links are a valuable resource that could bottlenecked when flooded with unnecessary cross-socket snoop requests. There's also considerably higher memory bandwidth with Skylake which can impact performance. As a compromise, the previous four snoop modes (no-snoop, early snoop, home snoop, and directory) have been reduced to just directory-base coherency. This also alleviates the implementation complex (which is already complex enough in itself).
 
−
 
−
[[File:snc clusters.png|right|350px]]
 
−
It should be pointed out that the directory-base coherency optimizations that were done in previous generations have been furthered improved with Skylake - particularly OSB, {{intel|HitME}} cache, IO directory cache. Skylake maintained support for {{intel|Opportunistic Snoop Broadcast}} (OSB) which allows the network to opportunistically make use of the UPI links when idle or lightly loaded thereby avoiding an expensive memory directory lookup. With the mesh network and distributed CHAs, HitME is now distributed and scales with the CHAs, enhancing the speeding up of cache-to-cache transfers (Those are your migratory cache lines that frequently get transferred between nodes). Specifically for I/O operations, the I/O directory cache (IODC), which was introduced with {{intel|Haswell|l=arch}}, improves stream throughput by eliminating directory reads for InvItoE from snoopy caching agent. Previously this was implemented as a 64-entry directory cache to complement the directory in memory. In Skylake, with a distributed CHA at each node, the IODC is implemented as an eight-entry directory cache per CHA.
 
−
 
−
==== Sub-NUMA Clustering ====
 
−
In previous generations Intel had a feature called {{intel|cluster-on-die}} (COD) which was introduced with {{intel|Haswell|l=arch}}. With Skylake, there's a similar feature called {{intel|sub-NUMA cluster}} (SNC). With a memory controller physically located on each side of the die, SNC allows for the creation of two localized domains with each memory controller belonging to each domain. The processor can then map the addresses from the controller to the distributed home ages and LLC in its domain. This allows executing code to experience lower LLC and memory latency within its domain compared to accesses outside of the domain.
 
−
 
−
It should be pointed out that in contrast to COD, SNC has a unique location for every adddress in the LCC and is evenr duplicated across LLC banks (previously, COD cache lines could have copies). Additionally, on multiprocessor system, address mapped to memory on remote sockets are still uniformally distributed across all LLC banks irrespective of the localized SNC domain.
 
−
 
−
=== Scalability ===
 
−
{{see also|intel/quickpath interconnect|intel/ultra path interconnect|l1=QuickPath Interconnect|l2=Ultra Path Interconnect}}
 
−
In the last couple of generations, Intel has been utilizing {{intel|QuickPath Interconnect}} (QPI) which served as a high-speed point-to-point interconnect. QPI has been replaced the {{intel|Ultra Path Interconnect}} (UPI) which is higher-efficiency coherent interconnect for scalable systems, allowing multiple processors to share a single shared address space. Depending on the exact model, each processor can have either either two or three UPI links connecting to the other processors.
 
−
 
−
UPI links eliminate some of the scalability limited that surfaced in QPI. They use directory-based home snoop coherency protocol and operate at up either 10.4 GT/s or 9.6 GT/s. This is quite a bit different form previous generations. In addition to the various improvements done to the protocol layer, {{intel|Skylake SP|l=arch}} now implements a distributed CHA that is situated along with the LLC bank on each core. It's in charge of tracking the various requests form the core as well as responding to snoop requests from both local and remote agents. The ease of distributing the home agent is a result of Intel getting rid of the requirement on preallocation of resources at the home agent. This also means that future architectures should be able to scale up well.
 
−
 
−
Depending on the exact model, Skylake processors can scale from 2-way all the way up to 8-way multiprocessing. Note that the high-end models that support 8-way multiprocessing also only come with three UPI links for this purpose while the lower end processors can have either two or three UPI links. Below are the typical configurations for those processors.
 
−
 
−
 
−
<div style="display: inline-block;">
 
−
<div style="float: left; margin: 15px; text-align: center;">'''2-way SMP; 2 UPI links'''<br><br>[[File:skylake sp 2-way 2 upi.svg|400px]]</div>
 
−
<div style="float: left; margin: 15px; text-align: center;">'''2-way SMP; 3 UPI links'''<br><br>[[File:skylake sp 2-way 3 upi.svg|400px]]</div>
 
−
</div>
 
−
 
−
 
−
<div style="display: inline-block;">
 
−
<div style="float: left; margin: 15px; text-align: center;">'''4-way SMP; 2 UPI links'''<br><br>[[File:skylake sp 4-way 2 upi.svg|400px]]</div>
 
−
<div style="float: left; margin: 15px; text-align: center;">'''4-way SMP; 3 UPI links'''<br><br>[[File:skylake sp 4-way 3 upi.svg|400px]]</div>
 
−
</div>
 
−
 
−
 
−
<div style="display: inline-block;">
 
−
<div style="text-align: center;">'''8-way SMP; 3 UPI links'''<br><br>[[File:skylake sp 8-way 3 upi.svg|400px]]</div>
 
−
</div>
 
−
 
−
=== Integrated Omni-Path ===
 
−
{{see also|intel/omni-path|l1=Intel's Omni-Path}}
 
−
[[File:omni-path ift carrier.png|thumb|right|300px|IFT (Internal Faceplate Transition) Carrier]]
 
−
A number of {{intel|Skylake SP|l=core}} models (specifically those with the "''F''" suffix) incorporate the {{intel|Omni-Path}} Host Fabric Interface (HFI) on-package. This was previously done with the {{intel|Knights Landing|l=arch}} ("''F''" suffixed) models. This, in addition to improving cost and power efficiencies, also eliminates the dependency on the x16 PCIe lanes on the motherboard. With the HFI on package, the chip can be plugged in directly to the IFT (Internal Faceplate Transition) carrier via a separate IFP (Internal Faceplate-to-Processor) 1-port cable (effectively a [[Twinax cable]]).
 
−
 
−
 
−
:: [[File:skylake sp with hfi to carrier.png|600px]]
 
−
 
−
{{clear}}
 
  
 
== New Technologies ==
 
== New Technologies ==

Revision as of 08:13, 21 July 2017

Edit Values
Skylake µarch
General Info
Arch TypeCPU
DesignerIntel
ManufacturerIntel
IntroductionAugust 5, 2015
Process14 nm
Core Configs2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28
Pipeline
TypeSuperscalar
OoOEYes
SpeculativeYes
Reg RenamingYes
Stages14-19
Instructions
ISAx86-16, x86-32, x86-64
ExtensionsMOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA3, F16C, BMI, BMI2, VT-x, VT-d, TXT, TSX, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVE, SGX, MPX, AVX-512
Cache
L1I Cache32 KiB/core
8-way set associative
L1D Cache32 KiB/core
8-way set associative
L2 Cache256 KiB/core
4-way set associative
L3 Cache2 MiB/core
Up to 16-way set associative
Side Cache128 MiB/package
on Iris Pro GPUs only
Cores
Core NamesSkylake Y,
Skylake U,
Skylake H,
Skylake S,
Skylake DT,
Skylake X,
Skylake SP
Succession

Skylake (SKL) is Intel's successor to Broadwell, a 14 nm process microarchitecture for mainstream desktops, servers, and mobile devices. Skylake succeeded the short-lived Broadwell which experienced severe delays. Skylake is the "Architecture" phase as part of Intel's PAO model. The microarchitecture was developed by Intel's R&D center in Haifa, Israel.

For desktop and mobile, Skylake is branded as 6th Generation Intel Core i3, Core i5, Core i7, and Core i9 processors. For workstations it's branded as Xeon E3 v5 For scalable server class processors, Intel branded it as Xeon Bronze, Xeon Silver, Xeon Gold, and Xeon Platinum.

Codenames

Core Abbrev Target
Skylake Y SKL-Y 2-in-1s detachable, tablets, and computer sticks
Skylake U SKL-U Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room
Skylake H SKL-H Ultimate mobile performance, mobile workstations
Skylake S SKL-S Desktop performance to value, AiOs, and minis
Skylake X SKL-X High-end desktops & enthusiasts market
Skylake DT SKL-DT Workstations & entry-level servers
Skylake SP SKL-SP Server Scalable Processors

Brands

New Xeon branding

Intel released Skylake under 7 main brand families.

Additionally, Intel introduced a number of new server chip families with the introduction of Skylake SP.

Logo Family General Description Differentiating Features
Cores HT AVX AVX2 AVX-512 TBT ECC
intel celeron (2015).png Celeron Entry-level Budget dual ✘ ✘ ✘ ✘ ✘ ✘
Entry-level Budget (Embedded) ✘ ✘ ✘ ✘ ✘ ✔
intel pentium (2015).png Pentium Budget (Mobile) dual ✔ ✘ ✘ ✘ ✘ ✘
Budget (Desktop) ✘ ✘ ✘ ✘ ✘ ✔
core i3 logo (2015).png Core i3 Low-end Performance dual ✔ ✔ ✔ ✘ ✘ ✘
Low-end Performance
(Desktop/Embedded) 		✔ ✔ ✔ ✘ ✘ ✔
core i5 logo (2015).png Core i5 Mid-range Performance dual ✔ ✔ ✔ ✘ ✔ ✘
quad ✘ ✔ ✔ ✘ ✔ ✘
core i7 logo (2015).png Core i7 High-end Performance dual ✔ ✔ ✔ ✘ ✔ ✘
quad ✔ ✔ ✔ ✘ ✔ ✘
Enthusiasts/High Performance (X) 6 - 8 ✔ ✔ ✔ ✔ ✔ ✘
xeon logo (2015).png Xeon E3 Workstation/dense servers quad ✔/✘ ✔ ✔ ✘ ✔ ✔
core i9x logo.png Core i9 Enthusiasts/High Performance 10 - 18 ✔ ✔ ✔ ✔ ✔ ✘
Logo Family General Description Differentiating Features
Cores HT TBT AVX-512 AVX-512 Units UPI links Scalability
xeon bronze (2017).png Xeon Bronze Entry-level performance /
Cost-sensitive 		6 - 8 ✘ ✘ ✔ 1 2 Up to 2
xeon silver (2017).png Xeon Silver Mid-range performance /
Efficient lower power 		4 - 12 ✔ ✔ ✔ 1 2 Up to 2
xeon gold (2017).png Xeon Gold 5000 High performance 4 - 14 ✔ ✔ ✔ 1 2 Up to 4
Xeon Gold 6000 Higher performance 6 - 22 ✔ ✔ ✔ 2 3 Up to 4
xeon platinum (2017).png Xeon Platinum Highest performance / flexibility 4 - 28 ✔ ✔ ✔ 2 3 Up to 8

Release Dates

Skylake was first demonstrated at the 2014 Intel Developer Forum in San Francisco on September 9 with the goals of launching in the second half of 2015. Skylake-based Core X was introduced in May 2017 while Skylake SP was introduced in July 2017.

Process Technology

Main article: Broadwell § Process Technology

Skylake uses the same 14 nm process used for the Broadwell microarchitecture for all mainstream consumer parts (Core, Celeron, et al). Unlike mainstream Skylake models, the enthusiasts (Skylake X) models are fabricated on Intel's enhanced 14+ nm process which is used by Kaby Lake (see Kaby Lake § Process Technology for more info).

Compatibility

Vendor OS Version Notes
Microsoft Windows Windows Vista No Support
Windows 7 Support ends July 2017
Windows 8.1
Windows 10 Support
Linux Linux Kernel 3.19 Initial Support (MPX support)
Google Chromium Chromium Support
Wind River VxWorks VxWorks 5.5? Support

Compiler support

Compiler Arch-Specific Arch-Favorable
ICC -march=skylake -mtune=skylake
GCC -march=skylake -mtune=skylake
LLVM -march=skylake -mtune=skylake
Visual Studio /arch:AVX2 /tune:skylake

CPUID

Core Extended
Family 		Family Extended
Model 		Model
Y/U 0 0x6 0x4 0xE
Family 6 Model 78
DT/H/S/X 0 0x6 0x5 0xE
Family 6 Model 94
SP 0 0x6 0x5 0x5
Family 6 Model 85

Architecture

Overall Skylake builds upon Intel's previous microarchitecture, Broadwell, but includes a wider and more beefed up front end, more optimized execution engine, and numerous other enhancements. Intel designed Skylake to encompass a wide range of devices and applications with a large emphasis on mobile with models ranging from as low as 4.5 W to as high as 100 W.

Key changes from Broadwell

skylake buff window.png
  • 8x performance/watt over Nehalem (Up from 3.5x in Haswell)
  • Mainstream chipset
    • Lynx Point → Sunrise Point
    • Bus/Interface to Chipset
      • DMI 3.0 (from 2.0)
        • Skylake S and Skylake H cores, connected by 4-lane DMI 3.0
        • Skylake Y and Skylake U cores have chipset in the same package (simplified OPIO)
        • Increase in transfer rate from 5.0 GT/s to 8.0 GT/s (~3.93GB/s up from 2GB/s) per lane
        • Limits motherboard trace design to 7 inches max from (down from 8) from the CPU to chipset
    • PCIe & DMI upgraded to Gen3
    • More I/O (configurable as PCIe/SATA/USB3)
    • Lower-power I/O (eMMC, UFS, SDXC)
    • CSI-2 for the integrated IPU (mobile SKUs)
    • Intel Sensor Solution Hub integration
  • System Agent
    • New Image Processing Unit (IPU)
    • Can now have its own variable voltage and frequency
  • Core
    • Front End
      • Larger legacy pipeline delivery (5 µOPs, up from 4)
        • Another simple decoder has been added.
      • Allocation Queue (IDQ)
        • Larger delivery (6 µOPs, up from 4)
        • 2.28x larger buffer (64/thread, up from 56)
        • Partitioned for each active threads (from unified)
      • Improved branch prediction unit
        • reduced penalty for wrong direct jump target
        • No specifics were disclosed
      • µOP Cache
        • instruction window is now 64 Bytes (from 32)
        • 1.5x bandwidth (6 µOPs/cycle, up from 4)
    • Execution Engine
      • Larger re-order buffer (224 entries, up from 192)
      • Larger scheduler (97 entries, up from 64)
        • Larger Integer Register File (180 entries, up from 168)
        • Larger Retire (4 µOPs/cycle/thread, up from 4 µOPs/cycle/core)?
    • Memory Subsystem
      • Larger store buffer (56 entries, up from 42)
      • L2$ was changed from 8-way to 4-way set associative
      • Page split load penalty reduced 20-fold
      • Larger Write-back buffer
      • Larger Line Fill Buffer?
  • Memory
    • Support for faster DDR-2400 memory
    • L3$ re-gained 512 KiB/core (See §eDRAM architectural changes for the reason)
    • A new coherent cache fabric implementation
      • doubles the throughput of the last level cache (LLC, L3$ in this case) miss handling
      • 50% improvement in bandwidth/watt
      • new eDRAM cache architecture for higher bandwidth
  • TLBs
    • ITLB
      • 4 KiB page translations was changed from 4-way to 8-way associative
    • STLB
      • 4 KiB + 2 MiB page translations was changed from 6-way to 12-way associative
  • Electrical
    • The fully integrated voltage regulator (FIVR) is moved back to the motherboard
      • Originally intended to be a cost-cutting measure by moving the FIVR on-die as well as making it more efficient, the move resulted in unintentionally making the FIVR the limiting factor when it came to overclocking.
    • DMI/PEG are now on a discrete clock domain with BCLK sitting on its own domain with full-range granularity (1 MHz intervals)
  • Testability
    • New support for Direct Connect Interface (DCI), a new debugging transport protocol designed to allow debugging of closed cases (e.g. laptops, embedded) by accessing things such as JTAG through any USB 3 port.
  • Gen 9 GPUs
    • Improved underlying implementation of the memory QoS for higher resolution displays and the integrated image signal processor (ISP)
      • Allow for higher concurrent bandwidth
    • Skylake retires VGA support, multi-monitor support for up to 3 displays via HDMI 1.4, DP 1.2, and eDP 1.3 interfaces.
    • Direct X 12, OpenCL 2.0, OpenGL 4.4
    • Up to 24 EUs GT2 (same as Haswell); 48 EUs for GT3, and up to 72 EUs on Iris Pro Graphics
      • 1,152 GFLOPS @ 1 GHz

Server

skylake sp buffer windows.png

Unlike client models, Skylake servers and HEDT models will still incorporate the fully integrated voltage regulator (FIVR) on-die. Those chips also have an entirely new multi-core architecture along with a new mesh topology interconnect network (from ring topology).

  • Improved "14 nm+" process (see Kaby Lake § Process Technology)
  • Omni-Path Architecture (OPA)
  • Mesh architecture
  • Core
    • Front-end
      • LSD is disabled
    • Back-end
      • Port 4 now performs 512b stores (from 256b)
      • Port 0 & Port 1 can now be fused to perform AVX-512
      • Port 5 now can do full 512b operations (not on all models)
    • Memory Subsystem
      • Store is now 64B/cycle (from 32B/cycle)
      • Load is now 2x64B/cycle (from 2x32B/cycle)
  • Memory
    • L2$
      • Increased to 1 MiB/core (from 250 KiB/core)
    • L3$
      • Was made non-inclusive (from inclusive)
      • Reduced to 1.375 MiB/core (from 2.5 MiB/core)
    • DRAM
      • hex-channel DDR4-2666 (from quad-channel)

CPU changes

  • Most ALU operations have 4 op/cycle 1 for 8 and 32-bit registers. 64-bit ops are still limited to 3 op/cycle. (16-bit throughput varies per op, can be 4, 3.5 or 2 op/cycle).
  • MOVSX and MOVZX have 4 op/cycle throughput for 16->32 and 32->64 forms, in addition to Haswell's 8->32, 8->64 and 16->64 bit forms.
  • ADC and SBB have throughput of 1 op/cycle, same as Haswell.
  • Vector moves have throughput of 4 op/cycle (move elimination).
  • Not only zeroing vector vpXORxx and vpSUBxx ops, but also vPCMPxxx on the same register, have throughput of 4 op/cycle.
  • Vector ALU ops are often "standardized" to latency of 4. for example, vADDPS and vMULPS used to have L of 3 and 5, now both are 4.
  • Fused multiply-add ops have latency of 4 and throughput of 0.5 op/cycle.
  • Throughput of vADDps, vSUBps, vCMPps, vMAXps, their scalar and double analogs is increased to 2 op/cycle.
  • Throughput of vPSLxx and vPSRxx with immediate (i.e. fixed vector shifts) is increased to 2 op/cycle.
  • Throughput of vANDps, vANDNps, vORps, vXORps, their scalar and double analogs, vPADDx, vPSUBx is increased to 3 op/cycle.
  • vDIVPD, vSQRTPD have approximately twice as good throughput: from 8 to 4 and from 28 to 12 cycles/op.
  • Throughput of some MMX ALU ops (such as PAND mm1, mm2) is decreased to 2 or 1 op/cycle (users are expected to use wider SSE/AVX registers instead).

New instructions

Skylake introduced a number of new instructions:

  • Client:
    • SGX1 - Software Guard Extensions, Version 1
    • MPX -Memory Protection Extensions
    • XSAVEC - Save processor extended states with compaction to memory
    • XSAVES - Save processor supervisor-mode extended states to memory.
    • CLFLUSHOPT - Flush & Invalidates memory operand and its associated cache line (All L1/L2/L3 etc..)
  • Server
    • (everything from Client)
    • AVX-512, specifically:
    • PKU - Memory Protection Keys for Userspace
    • PCOMMIT - PCOMMIT instruction
    • CLWB - CLWB instruction

Block Diagram

Client SoC

Entire SoC Overview (dual)

skylake soc block diagram (dual).svg

Entire SoC Overview (quad)

skylake soc block diagram.svg

Individual Core

skylake block diagram.svg

Gen9

See Gen9#Gen9.

Server MPUs

Server Chip

Note that the LCC die is identical without the two bottom rows. The XCC (28-core) die has one additional row and two additional columns of cores. Otherwise the die is identical. skylake sp hcc block diagram.svg

  • CHA - Caching and Home Agent
  • SF - Snooping Filter
Individual Core

skylake server block diagram.svg

Memory Hierarchy

Client

Other than a few organizational changes (e.g. L2$ went from 8-way to 4-way set associative), the overall memory structure is identical to Broadwell/Haswell.

  • Cache
    • L0 µOP cache:
      • 1,536 µOPs, 8-way set associative
        • 32 sets, 6-µOP line size
        • statically divided between threads, per core, inclusive with L1I
    • L1I Cache:
      • 32 KiB, 8-way set associative
        • 64 sets, 64 B line size
        • shared by the two threads, per core
    • L1D Cache:
      • 32 KiB, 8-way set associative
      • 64 sets, 64 B line size
      • shared by the two threads, per core
      • 4 cycles for fastest load-to-use (simple pointer accesses)
        • 5 cycles for complex addresses
      • 64 B/cycle load bandwidth
      • 32 B/cycle store bandwidth
      • Write-back policy
    • L2 Cache:
      • Unified, 256 KiB, 4-way set associative
      • 1024 sets, 64 B line size
      • Non-inclusive
      • 12 cycles for fastest load-to-use
      • 64 B/cycle bandwidth to L1$
      • Write-back policy
    • L3 Cache/LLC:
      • Up to 2 MiB Per core, shared across all cores
      • Up to 16-way set associative
      • Inclusive
      • 64 B line size
      • Write-back policy
      • Per each core:
        • Read: 32 B/cycle (@ ring clock)
        • Write: 32 B/cycle (@ ring clock)
      • 42 cycles for fastest load-to-use
    • Side Cache:
      • 64 MiB & 128 MiB eDRAM
      • Per package
      • Only on the Iris Pro GPUs
      • Read: 32 B/cycle (@ eDRAM clock)
      • Write: 32 B/cycle (@ eDRAM clock)
    • System DRAM:
      • 2 Channels
      • 8 B/cycle/channel (@ memory clock)
      • 42 cycles + 51 ns latency

Skylake TLB consists of dedicated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a unified L2 TLB (STLB).

  • TLBs:
    • ITLB
      • 4 KiB page translations:
        • 128 entries; 8-way set associative
        • dynamic partitioning
      • 2 MiB / 4 MiB page translations:
        • 8 entries per thread; fully associative
        • Duplicated for each thread
    • DTLB
      • 4 KiB page translations:
        • 64 entries; 4-way set associative
        • fixed partition
      • 2 MiB / 4 MiB page translations:
        • 32 entries; 4-way set associative
        • fixed partition
      • 1G page translations:
        • 4 entries; fully associative
        • fixed partition
    • STLB
      • 4 KiB + 2 MiB page translations:
        • 1536 entries; 12-way set associative
        • fixed partition
      • 1 GiB page translations:
        • 16 entries; 4-way set associative
        • fixed partition

Server

skylake x memory changes.png

The memory hierarchy for Skylake's server and HEDT processors has been rebalanced. Note that the L3 is now non-inclusive and some of the SRAM from the L3 cache was moved into the private L2 cache.

  • Cache
    • L2 Cache:
      • Unified, 1 MiB, 16-way set associative
      • 64 B line size
      • Non-inclusive
      • 64 B/cycle bandwidth to L1$
      • Write-back policy
      • 14 cycles latency
    • L3 Cache:
      • 1.375 MiB/s, shared across all cores
        • Note that some models have non-default cache sizes which are larger due to some disabled cores
      • 64 B line size
      • 11-way set associative
      • Non-Inclusive
      • Write-back policy
      • 50-70 cycles latency

Overview (Client)

Main article: Client Architecture

Skylake inherits much of the Core design philosophy which was enhanced significantly over the past number of architectures. Skylake, like its predecessor Broadwell, is also a dual-threaded and complex out-of-order pipeline. Skylake which builds on Broadwell incorporates large number of enhancements that has improved performance and efficiency in order to cover a large spectrum of devices from ultra-low power to high-performance computing. Additionally, a large number of improvements were done to the integrated graphics and multimedia capabilities as well as a new set of security technologies were introduced.

Design goals & new goals

skylake tdp-form factor range.png

Skylake tries to address 4 major design goals: Scalability, Performance, Power, and Media & Graphics. Skylake started out as a "traditional client product" when initial design goals and development started back in 2010. At that time, Skylake was expected to cover products ranging from thin-and-lights all the way up to desktops. This translated to roughly 3x TDP scale and 2x form factor between the smallest and biggest models. With the introduction of Ultralight, Skylake design goals were extended to a new class of smaller form factors (down to 15 W). Skylake design goals were later further extended to more mobility segments and even smaller form factors. The final end result is a microarchitecture that now spans 20-fold TDP scale (from 3.5 W all the way to 80 W+) and up to 4-fold form factor between the lowest power model and the highest performance model. Intel claims that Skylake also succeeded in reducing power by 40-60% during important workloads such as video, graphics, and idle power which especially affect models where battery life is absolutely critical.

It's interesting to note that Skylake's end result managed to overlap and to some degree exceed Intel's own ultra-low power (ULP) series of microarchitectures (i.e. Silvermont and Goldmont).

Product Development Vectors:

  • Form factor reduction - Emphasis was placed on reduction of form factor which includes both actual die size and package size.
  • Platform minimization - Effort was spent on reducing the overall platform size include reduction of system board size, components, and power.
  • Better life scenario power reduction - (mobile segment) The reduction of power during critical workloads such as video playback, video conferencing, and various other multimedia applications where the CPU itself is mostly idle.
  • IA performance - Improvements to both power and performance of the CPU core
  • IGP performance - Improvement to both power and performance of the GPU
  • New Security technology - Better protection against hardware and software attacks

SoC design

skylake soc (superset features).png

The Skylake system on a chip consists of a five major components: CPU core, LLC, Ring interconnect, System agent, and the integrated graphics. The image shown on the right, presented by Intel at the Intel Developer Forum in 2015, represents a hypothetical model incorporating all available features Skylake has to offer (i.e. superset of features). Skylake features an improved core (see § Pipeline) with higher performance per watt and higher performance per clock. The number of cores depends on the model, but mainstream mobile models are typically dual-core while mainstream desktop models are typically quad-core with dual-core desktop models still offered for value models (e.g. Celeron). Accompanying the cores is the LCC (last level cache or L3$ as seen from the CPU perspective). On mainstream parts the LLC consists of 2 MiB for each core with lower amounts for value models. Connecting the cores together is the ring interconnect. The ring extends to the GPU and the system agent as well. Intel further optimized the ring in Skylake for low-power and higher bandwidth.

Accompanying the cores is the Gen9 integrated graphics unit which comes in a number of different tiers ranging from just 12 execution units (used in the ultra-low power models) all the way the GT4 (Gen9 § Pipeline) with 72 execution units boasting a peak performance of up to 2,534.4 GFLOPS (HF) / 1,267.2 GFLOPS (SP) on the highest-end workstation model. The two highest-tier models are also accompanied by dedicated eDRAM ranging from 64 GiB to 120 GiB in capacity. The eDRAM is packaged along with the SoC in the same package.

On the other side is the System Agent (SA) which houses the various functionality that's not directly related to the cores or graphics. Skylake features an upgraded integrated memory controller (IMC) with most mainstream models supporting faster memory and dual-channel DDR4. The SA in Skylake also includes the Display Controller which now supports higher resolution displays with up to three displays for all mainstream models.

The SA also incorporates up to 20 lanes of PCIe with lesser amounts depending on the model. Of the 20 lanes, x16 PCIe lanes are offered for an external dedicated graphics hookup with the other four lanes reserved for communication with the southbridge chipset over Intel's new proprietary DMI 3.0 bus. The upgrade from DMI 2.0 (used in previous architectures) to 3.0 increased the bandwidth by 60% (8.0 GT/s from 5). For some models where form factor is exceptionally critical, such as those used for ultralight device, the chipset is packaged along with the SoC utilizing an on-package-interconnect (OPI) instead.

The last component of the System Agent and an entirely new addition in Skylake is the Image Processing Unit (IPU) which incorporates an image signal processor (ISP) on-die. The IPU is only available on mobile models and was added in order to improve and streamline (i.e. form factor and consistent set of features and quality) the implementation and performance of tablets and 2-in-1s. Previously this would require the assistance of an external component and the implementations varied by designer.

Overview (Server)

Main article: Server Architecture
300px

Skylake-based servers have been entirely re-architected to meet the need for increased scalabiltiy and performance all while meeting power requirements. A superset model is shown on the right. Skylake-based servers are the first mainstream servers to make use of Intel's new mesh interconnect architecture, an architecture that was previously explored, experimented with, and enhanced with Intel's Phi many-core processors. Those processors are offered from 4 cores up to 28 cores with 8 to 56 threads. With Skylake, Intel now has a separate core architecture for those chips which incorporate a plethora of new technologies and features including support for the new AVX-512 instruction set extension.

All models incorporate 6 channels of DDR4 supporting up to 12 DIMMS for a total of 768 GiB (with extended models support 1.5 TiB). For I/O all models incorporate 48x (3x16) lanes of PCIe 3.0. There is an additional x4 lanes PCIe 3.0 reserved exclusively for DMI for the the Lewisburg chipset. For a selected number of models (specifically those with F suffix) have an Omni-Path Host Fabric Interface (HFI) on-package (see Integrated Omni-Path).

Skylake processors are designed for scalability, supporting 2-way, 4-way, and 8-way multiprocessing through Intel's new Ultra Path Interconnect (UPI) interconnect links, with two to three links being offered (see § Scalability). High-end models have node controller support allowing higher way (e.g., 32-way multiprocessing).

New Technologies

Client

Software Guard Extension (SGX)

Main article: Intel's Software Guard Extension

Software Guard Extension (SGX) is a new inter-software guard x86 extension that allows software in user-level mode to create isolated secure environments called "enclaves" for storing data or code. Data and code stored in enclaves are protected from external processes including code executing with higher privileges including the operating system or a hypervisor (including all forms of debugging).

Memory Protection Extension (MPX)

Main article: Intel's Memory Protection Extension

Memory Protection Extension (MPX) is a new x86 extension that offers a hardware-level bound checking implementation. This extension allows an application to define memory boundaries for allocated memory areas. The processors can then check all proceeding memory accesses against those boundaries to ensure accesses are not out of bound. A program accessing a boundary-marked buffer out of buffer will generate an exception.

Server

In addition to the client technologies, servers have a number of new technologies as well:

Key Protection Technology (KPT)

Key Protection Technology (KPT) is designed to help secure sensitive private keys in hardware at runtime. KPT augments QuickAssist Technology (QAT) hardware crypto accelerators with run-time storage of private keys using Intel's existing Platform Trust Technology (PTT), thereby allowing high throughput hardware security acceleration. The QAT accelerators are all integrated onto Intel's new Lewisburg chipset along with the Converged Security Manageability Engine (CSME) which implements Intel's PTT. The CSME is linked through a private hardware link that is invisible to x86 software and simple hardware probes.

Memory Protection Keys for Userspace (PKU)

Memory Protection Keys for Userspace (PKU also PKEYs) is an extension that provides a mechanism for enforcing page-based protections - all without requiring modification of the page tables when an application changes protection domains. PKU introduces 16 keys by re-purposing the 4 ignored bits from the page table entry.

Mode-Based Execute (MBE) Control

Mode-Based Execute (MBE) is an enhancement to the Extended Page Tables (EPT) that provides finer level of control of execute permissions. With MBE the previous Execute Enable (X) bit is turned into Excuse Userspace page (XU) and Execute Supervisor page (XS). The processor selects the mode based on the guest page permission. With proper software support, hypervisors can take advantage of this as well to ensure integrity of kernel-level code.

Power

"Speed Shift" (new power management)

Ever since the introduction of the modern power management unit on a microprocessor, it was effectively the role of the operating system to determine the desired operating frequency and voltage (i.e. a p-state) for the current workload. When the CPU utilization peaked, it was the role of the operating system to bump up the frequency to help cope with it. The issue has always been the limitation of the operating system. One such major limitation is the granularity of the operating system response time - usually in the 10s of milliseconds (anything lower than that would likely be too intensive and would not yield better result). A second major issue is that the operating system doesn't have an instantaneous observation of the microarchitectural behavior of the workload.

Intel introduced Speed Shift with Skylake, a new methodology for quickly alternating core frequencies in response to power loads. Intel introduced a new unit called Package Control Unit (PCU) which is effectively a full fledged microcontroller (containing power management logic and firmware) that collects and tracks many internal SoC statistics as well as external power telemetry (e.g. Psys and iMon). PCU is also capable of interfacing with the OS, BIOS, and DPTF. Speed Shift improves the performance of frequency shifting by off-loading the control from the operating system to the PCU.

Speed Shift effectively eliminates the need for the OS to manages the P-states - though it does have the final say (unless special exceptions occur such as thermal throttling). Intel calls this "autonomous P-state", allowing Speed Shift to kick in in a matter of just ~1 millisecond (whereas the operating system-based p-states control can be as slow as 30 ms). Speed Shift effectively reduces hitting peak frequency in around ~30 ms from over 100 ms (OS-based implementation as before). While Speed Shift is capable of full range shift by default, the operating system can set the minimum QoS, maximum frequency and power/performance hints when desired. The final result should be higher performance and specially higher responsiveness at power constrained form factors.

SpeedStep Technology Expansion

Main article: SpeedStep Technology

Prior to Skylake, SpeedStep had three major domains: Cores, Integrated Graphics, and Coherent Fabric. With Skylake, SpeedStep has been extended to a number of new domains, including the System Agent, Memory, and the eDRAM I/O. Depending on the bandwidth consumption, SpeedStep can now save energy by reducing frequency on the new domains.

Information from the new domains, including additional thermal skin temperature control information is now supplied to OEMs.

Power of System (Psys)

Psys (Power of System) is a way for the PCU to monitor the performance and the total platform power provided to the chip. The chip uses a number of autonomous algorithms (one for "Low Range" and one for "High Range"). The Low Range algorithm frequency is lowered to conserve energy. Algorithm is capable of overriding the low P state - a state calculated ever millisecond based on the active workload and system characteristics. The High Range algorithm deals with elevating frequency for the benefit of increase performance (at the cost of increase energy/inefficiency). The exact ratio of ΔPower/ΔPerformance ≤ αPreference can be finely controlled via the OS and user preferences.

Other Power Optimization

Skylake includes a number of additional power optimization changes:

  • AVX2 is now power gated - prior to Skylake, AVX2 was not power gated which meant it was susceptible to leakage. Starting with Skylake, those instruction are full power gated and turn off when not used.
  • Many older/legacy underused resources have been downscaled.
  • Various scenario-based power optimizations were done, including:
    • Idle power is reduced further
    • C1 state power reduction (improved dynamic capacitance Cdyn)
    • For specific tasks such as streaming, Skylake is capable of powering down certain components of the GPU maintaining power on to the critical components needed for that purpose.

Overall Skylake enjoys better performance/Watt per core for 8x performance/watt over Nehalem.

AVX2 Power Gating

In Skylake, AVX2 has been entirely power-gated. The motive for this change is derived from the fact that applications either make heavy use of AVX2 instructions or don't use it at all. Most programs seldomly use AVX2 for only a small number of instructions. This gave Intel the ability to completely power gate it when the core execute code that does not make use of those instructions. Skylake requires a warm-up time before instructions can execute at full rate (in the order of a couple of 10,000s of cycles depending on frequency). Executing a dummy AVX2 instruction some time prior to heavy AVX2 workloads to prepare the CPU can avoid this.

Clock domains

Skylake is divided into a number of clock domains, each controlling the clock frequency of their respective unit in the processor. All clock domains are some multiple of the [virtual] bus clock (BCLK).

  • BCLK - Bus/Base Clock - The system bus interface frequency (once upon a time referred to the actual FSB speed, it now serves as only a base clock reference for all other clock domains). The base clock is 100 MHz.
  • Core Clock - The frequency at which the core and the L1/L2 caches operate at. (Frequency depends on the model and is represented as a multiple of BCLK).
  • Ring Clock - The frequency at which the ring interconnect and LLC operate at. Data from/to the individual cores are read/written into the L3 at a rate of 32B/cycle operating at Ring Clock frequency.
  • IGP Clock - The frequency at which the integrated graphics (Gen9 GPU) operates at. Data from/to the GPU are read/written into the LLC at a rate of 64B/cycle operating at this frequency as well.
  • eDRAM Clock - The frequency at which the embedded DRAM operates at (only available for certain models). Data is read/written from/to the LLC at a rate of 32B/cycle operating at this frequency as well.
  • MemClk - Memory Clock - The frequency at which the system DRAM operates at. DRAM data is transfered at a rate of 8B/cycle operating at MemClk frequency.

skylake soc clock domain block diagram.svg

Overclocking

See also: Intel's XMP
Warning: Overclocking can result in better performance for many types of workloads but it does so by pushing the system beyond its rated specifications. This can reduce the life of the chip, affect system data integrity, reduce system stability, and cause system components to fail. [Edit]
skylake overclock models chipset.png

Skylake has improved overclocking capabilities greatly. Overclocking is generally done on unlocked parts such as the Core i7-6700K, Core i5-6600K, and the mobile Core i7-6820HK processor. Unlocked processors should be paired with a chipset such as the Z170 which offers the most overclocking capabilities such as unlocked BCLK, unlocked core ratio, unlocked memory ratio, unlocked GPU ratio, and voltage controls.

Skylake increased both the overclocking range and ratio granularity, allowing for much more finer overclocking.

 Core i7-3770KCore i7-4790KCore i7-6700K
Core Ratios OverrideUp to x63Up to x80Up to x83
Real-time Core Ratio✔✔✔
BCLK OverclockingLimited100/125/167 MHz100+ in 1 MHz increments
MSR Voltage ControlSVID Extra VoltageFIVR SVID Extra Voltage, Voltage Override, InterpolativeSVID Extra Voltage, Voltage Override, Interpolative
GPU OverclockingAll ChipsetsAll ChipsetsAll Chipsets
DDR Ratio/Frequency Override and MRCUp to 2667 MT/sUp to 2667 MT/sUp to 4133 MT/s
DDR Granularity Steps200/266 MHz200/266 MHz100/133 MHz

Note that core ratio has been increased to a [theoretical] x83 multiplier and the coarse-grain ratio was dropped from Skylake allowing a BCLK ratio to have granularity of 1 MHz increments with BCLK frequency of over 200 readily achievable. The FIVER was removed and the voltage control was given back to the motherboard manufacturers; i.e., voltage supplies can be entirely motherboard-controlled. Skylake also bumped the DDR ratio up to 4133 MT/s.

skylake bclk.png

In the diagram on the left (xC) refers to the Core Frequency and is represented as a multiple of BCLK (Core Frequency = BCLK × Core Freq Multiplier up to x83). Likewise (xM) refers to the memory ratio (up to 4133 MT/s) and (xG) refers to the Graphics Frequency (pGfx; up to x60).

The BCLK in Skylake has undergone dramatic architectural changes. Considerable effort was dedicated to separating the DMI and PEG (PCIe & Graphics), allowing DMI/PEG to run at their nominal ~100 MHz clock in their own isolated clock domain. This allows BCLK to run at very high speeds (200 MHz+ with upward of 400 MHz+ in LN2). Additionally, while the BCLK is typically supplied by the chipset internal clock generator, it's also possible to supply the clock externally; i.e., motherboard ODMs can potentially take advantage of this and offer their own discrete BCLK control.

skylake bclk block.png
skylake vrails.png

Overclocking may involve changing the BCLK frequency. Because a large number of components operate their own clock domains as a multiple of the BCLK, an increase of 10% to the BCLK frequency will result in an increase of 10% to all other components. On Skylake, the PCIe & DMI sit on their own dedicated reference clock.

The primary voltage rails on Skylake are the VCORE = VRING which can operate up to 1.52 V (SVID) + Vboost. VDDQ is the typical 1.2 V nominal voltage for DDR4. VGT refers to the graphics processor which can also operate up to 1.52 V (SVID) + Vboost. Lastly the VSA refers to the system agent which has its own voltage control as well. Note that the ring voltage now runs at core voltage; Intel found no harm in overclocking and coupling them together. Additional rails are provided to the manufacturers which they can also expose for overclocking.

Voltage Control Modes

skylake pcu.png

As with all of Intel's latest microarchitectures, Skylake incorporates a Power Control Unit (PCU) which is a dedicated microcontroller on-die in the System Agent. The PCU runs dedicated embedded firmware and makes dynamic power management decisions based on various global inputs such as temperature, current, power, and workload types.

The system can operate in a number of Voltage Control Modes. The mode chosen dictates how the PCU determines what voltage to use:

  • Fused V/f - This is the default mode where the PCU will adjust the voltage based on frequency with a voltage cap at the max turbo frequency.
  • Interpolation (adaptive) V/f - In this mode a higher custom voltage point (e.g., 1.5 V) can be set. The PCU will then continue to increase voltage with frequency in a granular way up to the custom point. Likewise, if the frequency drops (e.g. when the system is idle) the voltage is reduced. This mode helps prolong the life of the chip by reducing the voltage when not needed.
  • Offset V/f - An offset mode allows the entire voltage curve to be shifted up by a certain amount. This mode can also be combined with any other mode to increase its entire curve by a certain millivoltage.
  • Override V/f - Override is an extreme overclocking mode whereby the system runs at a fixed voltage the entire time.

New Integration

Image Processing Unit (IPU)

Skylake integrates a new Image Processing Unit (IPU) on-die. The IPU is an entire imaging subsystem turnkey solution (i.e., ISP + hardware manipulation functionality), requiring only the external sensor camera. This feature is only available on the dual-core mobile models. The motivations behind this integration is primarily form factor the integrated IPU allows for higher user-end experience, and further power optimization.

skylake ipu.png

The IPU hardware supports:

  • 13 MP zero shutter lag 1080p60/2160p30 video capture and imaging and a large array of standardized image processing capabilities.
  • Face detection and recognition (smile/blink/group setting)
  • Full resolution still capture during video captures
  • Multi-stream video captures (up to 2 concurrent streams)
  • Panorama
  • Burst Captures
  • HDR ultra low-light captures

Graphics

Main article: Gen9

Support for three displays via HDMI 1.4[graphics 1], DisplayPort (DP) 1.2, an Embedded DisplayPort (eDP) 1.4 interfaces.

Gen9 IGP Models Standards
Name Execution Units Tier Series eDRAM Vulkan Direct3D OpenGL OpenCL
Windows Linux Windows Linux HLSL Windows Linux Windows Linux
HD Graphics 510 12 GT1 U, S - 1.0 12 N/A 5.1 4.5 4.5 2.0
HD Graphics 515 24 GT2 Y -
HD Graphics 520 24 GT2 U -
HD Graphics 530 24 GT2 H, S -
HD Graphics P530 24 GT2 H -
Iris Graphics 540 48 GT3e U 64 MiB
Iris Graphics 550 48 GT3e U 64 MiB
Iris Pro Graphics P555 48 GT3e H 128 MiB
Iris Pro Graphics 580 72 GT4e H 128 MiB
Iris Pro Graphics P580 72 GT4e H 128 MiB
  1. ↑ Note that while there is no native HDMI 2.0 support, Intel did provide somewhat of an awkward solution using an LSPCON (Level Shifter/Protocol Converter) to drive DP to HDMI 1.4 signal + convert HDMI 1.4 to HDMI 2.0. One such solution is the MegaChips MCDP2800.

Hardware Accelerated Video

[Edit] Skylake (Gen9) Hardware Accelerated Video Capabilities
Codec Encode Decode
Profiles Levels Max Resolution Profiles Levels Max Resolution
MPEG-2 (H.262) Main High 1080p (FHD) Main Main, High 1080p (FHD)
MPEG-4 AVC (H.264) High, Main 5.1 2160p (4K) Main, High, SHP, MHP 5.1 2160p (4K)
JPEG/MJPEG Baseline - 16k x 16k Baseline Unified 16k x 16k
HEVC (H.265) Main 5.1 2160p (4K) Main, Main 10 5.1 2160p (4K)
VC-1 ✘ Advanced, Main, Simple 3, High 3840x3840
VP8 Unified Unified - 0 Unified 1080p
VP9 ✘ 0 Unified 2160p (4K)

Sockets/Platform

Skylake Y and U are single-chip solutions. Y chips utilize a 2-die multi-chip package (MCP) whereas the Skylake U's are either 2 or 3-die MCP configuration. The 3 die chip configuration are for the Iris IGPs which incorporate an on-package cache (OPC) in addition to the hub. Communication from the CPU to the hub on those chips are done via a lightweight On-Package Interconnect (OPI) interface. Skylake S and H are a two-chip solution linked together via Intel's standard DMI 3.0 bus interface which utilizes 4 of the CPU's 20 PCIe 3.0 lanes (having a transfer rate of 8 GT/s per lane). Only Skylake S (used on mainstream desktop processors) are not soldered onto the motherboard and can be interchanged/replaced.

Core Socket Permanent Platform Chipset Bus
skylake y (back).png Skylake Y BGA-1515 Yes 1-chip N/A OPI
skylake u (back; standard).png Skylake U BGA-1356 Yes 1-chip
skylake h (back).png Skylake H BGA-1440 Yes 2-chip Sunrise Point DMI 3.0
skylake s (back).png Skylake S LGA-1151 No 2-chip
Skylake DT LGA-1151 No 2-chip Xeon Sunrise Point
skylake x (back).png Skylake X LGA-2066 No 2-chip Lewisburg

Packages

Core Die Type Package Dimensions
Skylake H 4+2 FCBGA-1440 42 mm x 28 mm x 1.46 mm
Skylake H 2+2
Skylake S 4+2 FCLGA-1151 37.5 mm x 37.5 mm x 4.4 mm
Skylake S 2+2

Die

Client Die

Skylake desktop and mobile come and 2 and 4 cores. Each variant has its own die. One of the most noticeable changes on die is the amount of die space allocated to the GPU. The major components of the die is:

  • System Agent
  • CPU Core
  • Ring bus interconnect
  • Memory Controller

System Agent

The System Agent (SA) contains the Image Processing Unit (IPU), the Display Engine (DE), the I/O bus and various other shared functionality. Note that the mainstream desktop (i.e., quad-core die) does not have an IPU (The memory controller actually occupies a portion of where it would otherwise be).

Dual-Core Die

skylake 2c sa.png
skylake 2c sa (annotated).png

Quad-Core Die

skylake 4c sa.png
skylake 4c sa (annotated).png

Core

Skylake Client models come in either 2x core or 4x core setup.

  • ~3.95 mm x ~2.21 mm
  • ~8.73 mm²
skylake core die.png


skylake core die (annotated).png

Core Group

Client models come in groups of 2 or 4 cores. (die sizes includes the dark silicon space where the L3 ends).

  • 2-cores group:
  • ~8.91 mm x ~2.845 mm
  • ~25.347 mm²
skylake 2x core complex die.png


  • 4-core group
  • ~8.844 mm x 5.694 mm
  • ~50.354 mm²
skylake 4x core complex die.png


Integrated Graphics

The integrated graphics takes up the largest portion of the die. The normal dual-core and quad-core dies come with 24 EU Gen9.5 GPU (with 12 units disabled on the low end models).

skylake gpu.png
skylake gpu (annotated).png

Dual-core

Die shot of the dual-core GT2 Skylake processors. Those are found in mobile models, and entry-level/budget processors:

  • 14 nm process
  • 11 metal layers
  • ~1,750,000,000 transistors
  • ~9.57 mm x ~10.3 mm
  • ~98.57 mm² die size
  • 2 CPU cores + 24 GPU EUs
skylake (dual core).png


skylake (dual core) (annotated).png

Quad-core

Die shot of the quad-core GT2 Skyllake processors. Those are found in almost all mainstream desktop processors.

  • 14 nm process
  • 11 metal layers
  • ~122 mm² die size
  • 4 CPU cores + 24 GPU EUs
skylake (quad-core).png


skylake (quad-core) (annotated).png

Server Die

Skylake SP chips and wafer.

Skylake Server class models and high-end desktop (HEDT) consist of 3 different dies: Low Core Count (LCC), High Core Count (HCC), and Extreme Core Count (XCC).

Low Core Count (LCC)

High Core Count (HCC)

Die shot of the octadeca core HEDT Skylake X processors.


skylake (octadeca core).png
Symbol version future.svg Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.


skylake (octadeca core) (annotated).png

Extreme Core Count (XCC)

skylake-sp xcc die shot.png


Symbol version future.svg Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.


skylake-sp xcc die shot (annotated).png

All Skylake Chips

 List of Skylake Processors
 Main processorTurbo BoostMemIGPMajor Feature Diff
ModelLaunchedPriceFamilyCore NameCoresThreadsL2$L3$TDPFrequency1 Core2 Cores3 Cores4 CoresMax MemGPUFrequencyTurboTurboSMTAVX2TXTTSXvPro
 Uniprocessors
3855U27 December 2015$ 107.00
€ 96.30
£ 86.67
¥ 11,056.31
CeleronSkylake U220.5 MiB
512 KiB
524,288 B
4.882812e-4 GiB
2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
15 W
15,000 mW
0.0201 hp
0.015 kW
1.6 GHz
1,600 MHz
1,600,000 kHz
32 GiB
32,768 MiB
33,554,432 KiB
34,359,738,368 B
0.0313 TiB
HD Graphics 510300 MHz
0.3 GHz
300,000 KHz
900 MHz
0.9 GHz
900,000 KHz
✘✘✘✘✘✘
3955U27 December 2015$ 107.00
€ 96.30
£ 86.67
¥ 11,056.31
CeleronSkylake U220.5 MiB
512 KiB
524,288 B
4.882812e-4 GiB
2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
15 W
15,000 mW
0.0201 hp
0.015 kW
2 GHz
2,000 MHz
2,000,000 kHz
32 GiB
32,768 MiB
33,554,432 KiB
34,359,738,368 B
0.0313 TiB
HD Graphics 510300 MHz
0.3 GHz
300,000 KHz
900 MHz
0.9 GHz
900,000 KHz
✘✘✘✘✘✘
G390019 October 2015$ 42.00
€ 37.80
£ 34.02
¥ 4,339.86
CeleronSkylake S220.5 MiB
512 KiB
524,288 B
4.882812e-4 GiB
2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
51 W
51,000 mW
0.0684 hp
0.051 kW
2.8 GHz
2,800 MHz
2,800,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
HD Graphics 510350 MHz
0.35 GHz
350,000 KHz
950 MHz
0.95 GHz
950,000 KHz
✘✘✔✘✘✘
G3900E2 January 2016$ 107.00
€ 96.30
£ 86.67
¥ 11,056.31
CeleronSkylake H220.5 MiB
512 KiB
524,288 B
4.882812e-4 GiB
2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
35 W
35,000 mW
0.0469 hp
0.035 kW
2.4 GHz
2,400 MHz
2,400,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
HD Graphics 510350 MHz
0.35 GHz
350,000 KHz
950 MHz
0.95 GHz
950,000 KHz
✘✘✘✘✘✘
G3900T19 October 2015CeleronSkylake S220.5 MiB
512 KiB
524,288 B
4.882812e-4 GiB
2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
35 W
35,000 mW
0.0469 hp
0.035 kW
2.6 GHz
2,600 MHz
2,600,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
HD Graphics 510350 MHz
0.35 GHz
350,000 KHz
950 MHz
0.95 GHz
950,000 KHz
✘✘✔✘✘✘
G3900TE19 October 2015$ 42.00
€ 37.80
£ 34.02
¥ 4,339.86
CeleronSkylake S220.5 MiB
512 KiB
524,288 B
4.882812e-4 GiB
2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
35 W
35,000 mW
0.0469 hp
0.035 kW
2.3 GHz
2,300 MHz
2,300,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
HD Graphics 510350 MHz
0.35 GHz
350,000 KHz
950 MHz
0.95 GHz
950,000 KHz
✘✘✔✘✘✘
G3902E2 January 2016$ 107.00
€ 96.30
£ 86.67
¥ 11,056.31
CeleronSkylake H220.5 MiB
512 KiB
524,288 B
4.882812e-4 GiB
2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
25 W
25,000 mW
0.0335 hp
0.025 kW
1.6 GHz
1,600 MHz
1,600,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
HD Graphics 510350 MHz
0.35 GHz
350,000 KHz
950 MHz
0.95 GHz
950,000 KHz
✘✘✘✘✘✘
G392019 October 2015$ 52.00
€ 46.80
£ 42.12
¥ 5,373.16
CeleronSkylake S220.5 MiB
512 KiB
524,288 B
4.882812e-4 GiB
2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
51 W
51,000 mW
0.0684 hp
0.051 kW
2.9 GHz
2,900 MHz
2,900,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
HD Graphics 510350 MHz
0.35 GHz
350,000 KHz
950 MHz
0.95 GHz
950,000 KHz
✘✘✔✘✘✘
i3-6006U10 November 2016$ 281.00
€ 252.90
£ 227.61
¥ 29,035.73
Core i3Skylake U240.5 MiB
512 KiB
524,288 B
4.882812e-4 GiB
3 MiB
3,072 KiB
3,145,728 B
0.00293 GiB
15 W
15,000 mW
0.0201 hp
0.015 kW
2 GHz
2,000 MHz
2,000,000 kHz
32 GiB
32,768 MiB
33,554,432 KiB
34,359,738,368 B
0.0313 TiB
HD Graphics 520300 MHz
0.3 GHz
300,000 KHz
900 MHz
0.9 GHz
900,000 KHz
✘✔✔✘✘✘
i3-6098P27 December 2015$ 117.00
€ 105.30
£ 94.77
¥ 12,089.61
Core i3Skylake S240.5 MiB
512 KiB
524,288 B
4.882812e-4 GiB
3 MiB
3,072 KiB
3,145,728 B
0.00293 GiB
54 W
54,000 mW
0.0724 hp
0.054 kW
3.6 GHz
3,600 MHz
3,600,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
HD Graphics 510350 MHz
0.35 GHz
350,000 KHz
1,050 MHz
1.05 GHz
1,050,000 KHz
✘✔✔✘✘✘
i3-610027 September 2015$ 117.00
€ 105.30
£ 94.77
¥ 12,089.61
Core i3Skylake S240.5 MiB
512 KiB
524,288 B
4.882812e-4 GiB
3 MiB
3,072 KiB
3,145,728 B
0.00293 GiB
51 W
51,000 mW
0.0684 hp
0.051 kW
3.7 GHz
3,700 MHz
3,700,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
HD Graphics 530350 MHz
0.35 GHz
350,000 KHz
1,050 MHz
1.05 GHz
1,050,000 KHz
✘✔✔✘✘✘
i3-6100E12 October 2015$ 225.00
€ 202.50
£ 182.25
¥ 23,249.25
Core i3Skylake H240.5 MiB
512 KiB
524,288 B
4.882812e-4 GiB
3 MiB
3,072 KiB
3,145,728 B
0.00293 GiB
35 W
35,000 mW
0.0469 hp
0.035 kW
2.7 GHz
2,700 MHz
2,700,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
HD Graphics 530350 MHz
0.35 GHz
350,000 KHz
950 MHz
0.95 GHz
950,000 KHz
✘✔✔✘✔✘
i3-6100H27 September 2015$ 225.00
€ 202.50
£ 182.25
¥ 23,249.25
Core i3Skylake H240.5 MiB
512 KiB
524,288 B
4.882812e-4 GiB
3 MiB
3,072 KiB
3,145,728 B
0.00293 GiB
35 W
35,000 mW
0.0469 hp
0.035 kW
2.7 GHz
2,700 MHz
2,700,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
HD Graphics 530350 MHz
0.35 GHz
350,000 KHz
900 MHz
0.9 GHz
900,000 KHz
✘✔✔✘✘✘
i3-6100T27 September 2015$ 117.00
€ 105.30
£ 94.77
¥ 12,089.61
Core i3Skylake S240.5 MiB
512 KiB
524,288 B
4.882812e-4 GiB
3 MiB
3,072 KiB
3,145,728 B
0.00293 GiB
35 W
35,000 mW
0.0469 hp
0.035 kW
3.2 GHz
3,200 MHz
3,200,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
HD Graphics 530350 MHz
0.35 GHz
350,000 KHz
950 MHz
0.95 GHz
950,000 KHz
✘✔✔✘✘✘
i3-6100TE12 October 2015$ 117.00
€ 105.30
£ 94.77
¥ 12,089.61
Core i3Skylake S240.5 MiB
512 KiB
524,288 B
4.882812e-4 GiB
4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
35 W
35,000 mW
0.0469 hp
0.035 kW
2.7 GHz
2,700 MHz
2,700,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
HD Graphics 530350 MHz
0.35 GHz
350,000 KHz
1,000 MHz
1 GHz
1,000,000 KHz
✘✔✔✘✘✘
i3-6100U27 September 2015$ 281.00
€ 252.90
£ 227.61
¥ 29,035.73
Core i3Skylake U240.5 MiB
512 KiB
524,288 B
4.882812e-4 GiB
3 MiB
3,072 KiB
3,145,728 B
0.00293 GiB
15 W
15,000 mW
0.0201 hp
0.015 kW
2.3 GHz
2,300 MHz
2,300,000 kHz
32 GiB
32,768 MiB
33,554,432 KiB
34,359,738,368 B
0.0313 TiB
HD Graphics 520300 MHz
0.3 GHz
300,000 KHz
1,000 MHz
1 GHz
1,000,000 KHz
✘✔✔✘✘✘
i3-6102E12 October 2015$ 225.00
€ 202.50
£ 182.25
¥ 23,249.25
Core i3Skylake H240.5 MiB
512 KiB
524,288 B
4.882812e-4 GiB
3 MiB
3,072 KiB
3,145,728 B
0.00293 GiB
25 W
25,000 mW
0.0335 hp
0.025 kW
1.9 GHz
1,900 MHz
1,900,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
HD Graphics 530350 MHz
0.35 GHz
350,000 KHz
950 MHz
0.95 GHz
950,000 KHz
✘✔✔✘✔✘
i3-6120TCore i3Skylake S240.5 MiB
512 KiB
524,288 B
4.882812e-4 GiB
3 MiB
3,072 KiB
3,145,728 B
0.00293 GiB
35 W
35,000 mW
0.0469 hp
0.035 kW
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
HD Graphics 530350 MHz
0.35 GHz
350,000 KHz
950 MHz
0.95 GHz
950,000 KHz
✘✔✔✘✘✘
i3-6157UJune 2016$ 304.00
€ 273.60
£ 246.24
¥ 31,412.32
Core i3Skylake U240.5 MiB
512 KiB
524,288 B
4.882812e-4 GiB
3 MiB
3,072 KiB
3,145,728 B
0.00293 GiB
28 W
28,000 mW
0.0375 hp
0.028 kW
2.4 GHz
2,400 MHz
2,400,000 kHz
32 GiB
32,768 MiB
33,554,432 KiB
34,359,738,368 B
0.0313 TiB
Iris Graphics 550300 MHz
0.3 GHz
300,000 KHz
1,000 MHz
1 GHz
1,000,000 KHz
✘✔✔✘✘✘
i3-6167U27 September 2015$ 304.00
€ 273.60
£ 246.24
¥ 31,412.32
Core i3Skylake U240.5 MiB
512 KiB
524,288 B
4.882812e-4 GiB
3 MiB
3,072 KiB
3,145,728 B
0.00293 GiB
28 W
28,000 mW
0.0375 hp
0.028 kW
2.7 GHz
2,700 MHz
2,700,000 kHz
32 GiB
32,768 MiB
33,554,432 KiB
34,359,738,368 B
0.0313 TiB
Iris Graphics 550300 MHz
0.3 GHz
300,000 KHz
1,000 MHz
1 GHz
1,000,000 KHz
✘✔✔✘✘✘
i3-630027 September 2015$ 147.00
€ 132.30
£ 119.07
¥ 15,189.51
Core i3Skylake S240.5 MiB
512 KiB
524,288 B
4.882812e-4 GiB
4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
51 W
51,000 mW
0.0684 hp
0.051 kW
3.8 GHz
3,800 MHz
3,800,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
HD Graphics 530350 MHz
0.35 GHz
350,000 KHz
1,150 MHz
1.15 GHz
1,150,000 KHz
✘✔✔✘✘✘
i3-6300T27 September 2015$ 147.00
€ 132.30
£ 119.07
¥ 15,189.51
Core i3Skylake S240.5 MiB
512 KiB
524,288 B
4.882812e-4 GiB
4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
35 W
35,000 mW
0.0469 hp
0.035 kW
3.3 GHz
3,300 MHz
3,300,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
HD Graphics 530350 MHz
0.35 GHz
350,000 KHz
950 MHz
0.95 GHz
950,000 KHz
✘✔✔✘✘✘
i3-632027 September 2015$ 157.00
€ 141.30
£ 127.17
¥ 16,222.81
Core i3Skylake S240.5 MiB
512 KiB
524,288 B
4.882812e-4 GiB
4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
51 W
51,000 mW
0.0684 hp
0.051 kW
3.9 GHz
3,900 MHz
3,900,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
HD Graphics 530350 MHz
0.35 GHz
350,000 KHz
1,150 MHz
1.15 GHz
1,150,000 KHz
✘✔✔✘✘✘
i3-6320TCore i3Skylake S240.5 MiB
512 KiB
524,288 B
4.882812e-4 GiB
4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
35 W
35,000 mW
0.0469 hp
0.035 kW
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
HD Graphics 530350 MHz
0.35 GHz
350,000 KHz
950 MHz
0.95 GHz
950,000 KHz
✘✔✔✘✘✘
i5-6198DU27 December 2015Core i5Skylake U240.5 MiB
512 KiB
524,288 B
4.882812e-4 GiB
3 MiB
3,072 KiB
3,145,728 B
0.00293 GiB
15 W
15,000 mW
0.0201 hp
0.015 kW
2.3 GHz
2,300 MHz
2,300,000 kHz
2.8 GHz
2,800 MHz
2,800,000 kHz
32 GiB
32,768 MiB
33,554,432 KiB
34,359,738,368 B
0.0313 TiB
HD Graphics 510300 MHz
0.3 GHz
300,000 KHz
1,000 MHz
1 GHz
1,000,000 KHz
✔✔✔✘✘✘
i5-6200U27 September 2015$ 281.00
€ 252.90
£ 227.61
¥ 29,035.73
Core i5Skylake U240.5 MiB
512 KiB
524,288 B
4.882812e-4 GiB
3 MiB
3,072 KiB
3,145,728 B
0.00293 GiB
15 W
15,000 mW
0.0201 hp
0.015 kW
2.3 GHz
2,300 MHz
2,300,000 kHz
2.8 GHz
2,800 MHz
2,800,000 kHz
2.7 GHz
2,700 MHz
2,700,000 kHz
32 GiB
32,768 MiB
33,554,432 KiB
34,359,738,368 B
0.0313 TiB
HD Graphics 520300 MHz
0.3 GHz
300,000 KHz
1,000 MHz
1 GHz
1,000,000 KHz
✔✔✔✘✘✘
i5-6260U27 September 2015$ 304.00
€ 273.60
£ 246.24
¥ 31,412.32
Core i5Skylake U240.5 MiB
512 KiB
524,288 B
4.882812e-4 GiB
4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
15 W
15,000 mW
0.0201 hp
0.015 kW
1.8 GHz
1,800 MHz
1,800,000 kHz
2.9 GHz
2,900 MHz
2,900,000 kHz
2.7 GHz
2,700 MHz
2,700,000 kHz
32 GiB
32,768 MiB
33,554,432 KiB
34,359,738,368 B
0.0313 TiB
Iris Graphics 540300 MHz
0.3 GHz
300,000 KHz
950 MHz
0.95 GHz
950,000 KHz
✔✔✔✘✘✘
i5-6267U27 September 2015$ 304.00
€ 273.60
£ 246.24
¥ 31,412.32
Core i5Skylake U240.5 MiB
512 KiB
524,288 B
4.882812e-4 GiB
4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
28 W
28,000 mW
0.0375 hp
0.028 kW
2.9 GHz
2,900 MHz
2,900,000 kHz
3.3 GHz
3,300 MHz
3,300,000 kHz
3.1 GHz
3,100 MHz
3,100,000 kHz
32 GiB
32,768 MiB
33,554,432 KiB
34,359,738,368 B
0.0313 TiB
Iris Graphics 550300 MHz
0.3 GHz
300,000 KHz
1,050 MHz
1.05 GHz
1,050,000 KHz
✔✔✔✘✘✘
i5-6287U27 September 2015$ 304.00
€ 273.60
£ 246.24
¥ 31,412.32
Core i5Skylake U240.5 MiB
512 KiB
524,288 B
4.882812e-4 GiB
4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
28 W
28,000 mW
0.0375 hp
0.028 kW
3.1 GHz
3,100 MHz
3,100,000 kHz
3.5 GHz
3,500 MHz
3,500,000 kHz
3.3 GHz
3,300 MHz
3,300,000 kHz
32 GiB
32,768 MiB
33,554,432 KiB
34,359,738,368 B
0.0313 TiB
Iris Graphics 550300 MHz
0.3 GHz
300,000 KHz
1,100 MHz
1.1 GHz
1,100,000 KHz
✔✔✔✘✘✘
i5-6300HQ27 September 2015$ 250.00
€ 225.00
£ 202.50
¥ 25,832.50
Core i5Skylake H441 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
6 MiB
6,144 KiB
6,291,456 B
0.00586 GiB
45 W
45,000 mW
0.0603 hp
0.045 kW
2.3 GHz
2,300 MHz
2,300,000 kHz
3.2 GHz
3,200 MHz
3,200,000 kHz
3 GHz
3,000 MHz
3,000,000 kHz
2.9 GHz
2,900 MHz
2,900,000 kHz
2.8 GHz
2,800 MHz
2,800,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
HD Graphics 530350 MHz
0.35 GHz
350,000 KHz
950 MHz
0.95 GHz
950,000 KHz
✔✘✔✘✔✘
i5-6300U27 September 2015$ 281.00
€ 252.90
£ 227.61
¥ 29,035.73
Core i5Skylake U240.5 MiB
512 KiB
524,288 B
4.882812e-4 GiB
3 MiB
3,072 KiB
3,145,728 B
0.00293 GiB
15 W
15,000 mW
0.0201 hp
0.015 kW
2.4 GHz
2,400 MHz
2,400,000 kHz
3 GHz
3,000 MHz
3,000,000 kHz
2.9 GHz
2,900 MHz
2,900,000 kHz
32 GiB
32,768 MiB
33,554,432 KiB
34,359,738,368 B
0.0313 TiB
HD Graphics 520300 MHz
0.3 GHz
300,000 KHz
1,000 MHz
1 GHz
1,000,000 KHz
✔✔✔✔✔✔
i5-6350HQ2 January 2016$ 306.00
€ 275.40
£ 247.86
¥ 31,618.98
Core i5Skylake H441 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
6 MiB
6,144 KiB
6,291,456 B
0.00586 GiB
45 W
45,000 mW
0.0603 hp
0.045 kW
2.3 GHz
2,300 MHz
2,300,000 kHz
3.2 GHz
3,200 MHz
3,200,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
Iris Pro Graphics 580350 MHz
0.35 GHz
350,000 KHz
900 MHz
0.9 GHz
900,000 KHz
✔✘✔✘✘✘
i5-6360U27 September 2015$ 304.00
€ 273.60
£ 246.24
¥ 31,412.32
Core i5Skylake U240.5 MiB
512 KiB
524,288 B
4.882812e-4 GiB
4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
15 W
15,000 mW
0.0201 hp
0.015 kW
2 GHz
2,000 MHz
2,000,000 kHz
3.1 GHz
3,100 MHz
3,100,000 kHz
2.9 GHz
2,900 MHz
2,900,000 kHz
32 GiB
32,768 MiB
33,554,432 KiB
34,359,738,368 B
0.0313 TiB
Iris Graphics 540300 MHz
0.3 GHz
300,000 KHz
1,000 MHz
1 GHz
1,000,000 KHz
✔✔✔✔✔✔
i5-640027 September 2015$ 187.00
€ 168.30
£ 151.47
¥ 19,322.71
Core i5Skylake S441 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
6 MiB
6,144 KiB
6,291,456 B
0.00586 GiB
65 W
65,000 mW
0.0872 hp
0.065 kW
2.7 GHz
2,700 MHz
2,700,000 kHz
3.3 GHz
3,300 MHz
3,300,000 kHz
3.3 GHz
3,300 MHz
3,300,000 kHz
3.2 GHz
3,200 MHz
3,200,000 kHz
3.1 GHz
3,100 MHz
3,100,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
HD Graphics 530350 MHz
0.35 GHz
350,000 KHz
950 MHz
0.95 GHz
950,000 KHz
✔✘✔✘✘✘
i5-6400T27 September 2015$ 182.00
€ 163.80
£ 147.42
¥ 18,806.06
Core i5Skylake S441 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
6 MiB
6,144 KiB
6,291,456 B
0.00586 GiB
35 W
35,000 mW
0.0469 hp
0.035 kW
2.2 GHz
2,200 MHz
2,200,000 kHz
2.8 GHz
2,800 MHz
2,800,000 kHz
2.7 GHz
2,700 MHz
2,700,000 kHz
2.6 GHz
2,600 MHz
2,600,000 kHz
2.5 GHz
2,500 MHz
2,500,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
HD Graphics 530350 MHz
0.35 GHz
350,000 KHz
950 MHz
0.95 GHz
950,000 KHz
✔✘✔✘✘✘
i5-6402P27 December 2015$ 187.00
€ 168.30
£ 151.47
¥ 19,322.71
Core i5Skylake S441 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
6 MiB
6,144 KiB
6,291,456 B
0.00586 GiB
65 W
65,000 mW
0.0872 hp
0.065 kW
2.8 GHz
2,800 MHz
2,800,000 kHz
3.4 GHz
3,400 MHz
3,400,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
HD Graphics 510350 MHz
0.35 GHz
350,000 KHz
950 MHz
0.95 GHz
950,000 KHz
✔✘✔✘✘✘
i5-6440EQ12 October 2015$ 250.00
€ 225.00
£ 202.50
¥ 25,832.50
Core i5Skylake H441 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
6 MiB
6,144 KiB
6,291,456 B
0.00586 GiB
45 W
45,000 mW
0.0603 hp
0.045 kW
2.7 GHz
2,700 MHz
2,700,000 kHz
3.4 GHz
3,400 MHz
3,400,000 kHz
3.3 GHz
3,300 MHz
3,300,000 kHz
3.2 GHz
3,200 MHz
3,200,000 kHz
3.1 GHz
3,100 MHz
3,100,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
HD Graphics 530350 MHz
0.35 GHz
350,000 KHz
1,000 MHz
1 GHz
1,000,000 KHz
✔✘✔✔✔✔
i5-6440HQ27 October 2015$ 250.00
€ 225.00
£ 202.50
¥ 25,832.50
Core i5Skylake H441 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
6 MiB
6,144 KiB
6,291,456 B
0.00586 GiB
45 W
45,000 mW
0.0603 hp
0.045 kW
2.6 GHz
2,600 MHz
2,600,000 kHz
3.5 GHz
3,500 MHz
3,500,000 kHz
3.3 GHz
3,300 MHz
3,300,000 kHz
3.2 GHz
3,200 MHz
3,200,000 kHz
3.1 GHz
3,100 MHz
3,100,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
HD Graphics 530350 MHz
0.35 GHz
350,000 KHz
950 MHz
0.95 GHz
950,000 KHz
✔✘✔✔✔✔
i5-6442EQ12 October 2015$ 250.00
€ 225.00
£ 202.50
¥ 25,832.50
Core i5Skylake H441 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
6 MiB
6,144 KiB
6,291,456 B
0.00586 GiB
25 W
25,000 mW
0.0335 hp
0.025 kW
1.9 GHz
1,900 MHz
1,900,000 kHz
2.7 GHz
2,700 MHz
2,700,000 kHz
2.6 GHz
2,600 MHz
2,600,000 kHz
2.5 GHz
2,500 MHz
2,500,000 kHz
2.4 GHz
2,400 MHz
2,400,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
HD Graphics 530350 MHz
0.35 GHz
350,000 KHz
1,000 MHz
1 GHz
1,000,000 KHz
✔✘✔✔✔✔
i5-650027 September 2015$ 202.00
€ 181.80
£ 163.62
¥ 20,872.66
Core i5Skylake S441 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
6 MiB
6,144 KiB
6,291,456 B
0.00586 GiB
65 W
65,000 mW
0.0872 hp
0.065 kW
3.2 GHz
3,200 MHz
3,200,000 kHz
3.6 GHz
3,600 MHz
3,600,000 kHz
3.5 GHz
3,500 MHz
3,500,000 kHz
3.4 GHz
3,400 MHz
3,400,000 kHz
3.3 GHz
3,300 MHz
3,300,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
HD Graphics 530350 MHz
0.35 GHz
350,000 KHz
1,050 MHz
1.05 GHz
1,050,000 KHz
✔✘✔✔✔✔
i5-6500T27 September 2015$ 192.00
€ 172.80
£ 155.52
¥ 19,839.36
Core i5Skylake S441 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
6 MiB
6,144 KiB
6,291,456 B
0.00586 GiB
35 W
35,000 mW
0.0469 hp
0.035 kW
2.5 GHz
2,500 MHz
2,500,000 kHz
3.1 GHz
3,100 MHz
3,100,000 kHz
3 GHz
3,000 MHz
3,000,000 kHz
2.9 GHz
2,900 MHz
2,900,000 kHz
2.8 GHz
2,800 MHz
2,800,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
HD Graphics 530350 MHz
0.35 GHz
350,000 KHz
1,100 MHz
1.1 GHz
1,100,000 KHz
✔✘✔✔✔✔
i5-6500TE19 October 2015$ 192.00
€ 172.80
£ 155.52
¥ 19,839.36
Core i5Skylake S441 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
6 MiB
6,144 KiB
6,291,456 B
0.00586 GiB
35 W
35,000 mW
0.0469 hp
0.035 kW
2.3 GHz
2,300 MHz
2,300,000 kHz
3.3 GHz
3,300 MHz
3,300,000 kHz
3.2 GHz
3,200 MHz
3,200,000 kHz
3.1 GHz
3,100 MHz
3,100,000 kHz
3 GHz
3,000 MHz
3,000,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
HD Graphics 530350 MHz
0.35 GHz
350,000 KHz
1,000 MHz
1 GHz
1,000,000 KHz
✔✘✔✔✔✔
i5-6585R22 April 2016$ 255.00
€ 229.50
£ 206.55
¥ 26,349.15
Core i5Skylake H441 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
6 MiB
6,144 KiB
6,291,456 B
0.00586 GiB
65 W
65,000 mW
0.0872 hp
0.065 kW
2.8 GHz
2,800 MHz
2,800,000 kHz
3.6 GHz
3,600 MHz
3,600,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
Iris Pro Graphics 580350 MHz
0.35 GHz
350,000 KHz
1,100 MHz
1.1 GHz
1,100,000 KHz
✔✘✔✔✔✘
i5-660027 September 2015$ 224.00
€ 201.60
£ 181.44
¥ 23,145.92
Core i5Skylake S441 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
6 MiB
6,144 KiB
6,291,456 B
0.00586 GiB
65 W
65,000 mW
0.0872 hp
0.065 kW
3.3 GHz
3,300 MHz
3,300,000 kHz
3.9 GHz
3,900 MHz
3,900,000 kHz
3.8 GHz
3,800 MHz
3,800,000 kHz
3.7 GHz
3,700 MHz
3,700,000 kHz
3.6 GHz
3,600 MHz
3,600,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
HD Graphics 530350 MHz
0.35 GHz
350,000 KHz
1,150 MHz
1.15 GHz
1,150,000 KHz
✔✘✔✔✔✔
i5-6600K27 September 2015$ 243.00
€ 218.70
£ 196.83
¥ 25,109.19
Core i5Skylake S441 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
6 MiB
6,144 KiB
6,291,456 B
0.00586 GiB
91 W
91,000 mW
0.122 hp
0.091 kW
3.5 GHz
3,500 MHz
3,500,000 kHz
3.9 GHz
3,900 MHz
3,900,000 kHz
3.8 GHz
3,800 MHz
3,800,000 kHz
3.7 GHz
3,700 MHz
3,700,000 kHz
3.6 GHz
3,600 MHz
3,600,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
HD Graphics 530350 MHz
0.35 GHz
350,000 KHz
1,150 MHz
1.15 GHz
1,150,000 KHz
✔✘✔✘✔✘
i5-6600T27 September 2015$ 213.00
€ 191.70
£ 172.53
¥ 22,009.29
Core i5Skylake S441 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
6 MiB
6,144 KiB
6,291,456 B
0.00586 GiB
35 W
35,000 mW
0.0469 hp
0.035 kW
2.7 GHz
2,700 MHz
2,700,000 kHz
3.5 GHz
3,500 MHz
3,500,000 kHz
3.4 GHz
3,400 MHz
3,400,000 kHz
3.3 GHz
3,300 MHz
3,300,000 kHz
3.3 GHz
3,300 MHz
3,300,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
HD Graphics 530350 MHz
0.35 GHz
350,000 KHz
1,100 MHz
1.1 GHz
1,100,000 KHz
✔✘✔✔✔✔
i5-6685R22 April 2016$ 288.00
€ 259.20
£ 233.28
¥ 29,759.04
Core i5Skylake H441 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
6 MiB
6,144 KiB
6,291,456 B
0.00586 GiB
65 W
65,000 mW
0.0872 hp
0.065 kW
3.2 GHz
3,200 MHz
3,200,000 kHz
3.8 GHz
3,800 MHz
3,800,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
Iris Pro Graphics 580350 MHz
0.35 GHz
350,000 KHz
1,150 MHz
1.15 GHz
1,150,000 KHz
✔✘✔✔✔✘
i7-6498DU27 September 2015$ 393.00
€ 353.70
£ 318.33
¥ 40,608.69
Core i7Skylake U240.5 MiB
512 KiB
524,288 B
4.882812e-4 GiB
4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
15 W
15,000 mW
0.0201 hp
0.015 kW
2.5 GHz
2,500 MHz
2,500,000 kHz
3.1 GHz
3,100 MHz
3,100,000 kHz
32 GiB
32,768 MiB
33,554,432 KiB
34,359,738,368 B
0.0313 TiB
HD Graphics 510300 MHz
0.3 GHz
300,000 KHz
1,050 MHz
1.05 GHz
1,050,000 KHz
✔✔✔✘✘✘
i7-6500U27 September 2015$ 393.00
€ 353.70
£ 318.33
¥ 40,608.69
Core i7Skylake U240.5 MiB
512 KiB
524,288 B
4.882812e-4 GiB
4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
15 W
15,000 mW
0.0201 hp
0.015 kW
2.5 GHz
2,500 MHz
2,500,000 kHz
3.1 GHz
3,100 MHz
3,100,000 kHz
3 GHz
3,000 MHz
3,000,000 kHz
32 GiB
32,768 MiB
33,554,432 KiB
34,359,738,368 B
0.0313 TiB
HD Graphics 520300 MHz
0.3 GHz
300,000 KHz
1,050 MHz
1.05 GHz
1,050,000 KHz
✔✔✔✘✘✘
i7-6560U27 September 2015Core i7Skylake U240.5 MiB
512 KiB
524,288 B
4.882812e-4 GiB
4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
15 W
15,000 mW
0.0201 hp
0.015 kW
2.2 GHz
2,200 MHz
2,200,000 kHz
3.2 GHz
3,200 MHz
3,200,000 kHz
3.1 GHz
3,100 MHz
3,100,000 kHz
32 GiB
32,768 MiB
33,554,432 KiB
34,359,738,368 B
0.0313 TiB
Iris Graphics 540300 MHz
0.3 GHz
300,000 KHz
1,050 MHz
1.05 GHz
1,050,000 KHz
✔✔✔✘✘✘
i7-6567U27 September 2015Core i7Skylake U240.5 MiB
512 KiB
524,288 B
4.882812e-4 GiB
4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
28 W
28,000 mW
0.0375 hp
0.028 kW
3.3 GHz
3,300 MHz
3,300,000 kHz
3.6 GHz
3,600 MHz
3,600,000 kHz
3.4 GHz
3,400 MHz
3,400,000 kHz
32 GiB
32,768 MiB
33,554,432 KiB
34,359,738,368 B
0.0313 TiB
Iris Graphics 550300 MHz
0.3 GHz
300,000 KHz
1,100 MHz
1.1 GHz
1,100,000 KHz
✔✔✔✘✘✘
i7-6600U27 September 2015$ 393.00
€ 353.70
£ 318.33
¥ 40,608.69
Core i7Skylake U240.5 MiB
512 KiB
524,288 B
4.882812e-4 GiB
4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
15 W
15,000 mW
0.0201 hp
0.015 kW
2.6 GHz
2,600 MHz
2,600,000 kHz
3.4 GHz
3,400 MHz
3,400,000 kHz
3.2 GHz
3,200 MHz
3,200,000 kHz
32 GiB
32,768 MiB
33,554,432 KiB
34,359,738,368 B
0.0313 TiB
HD Graphics 520300 MHz
0.3 GHz
300,000 KHz
1,050 MHz
1.05 GHz
1,050,000 KHz
✔✔✔✔✔✔
i7-6650U27 September 2015$ 415.00
€ 373.50
£ 336.15
¥ 42,881.95
Core i7Skylake U240.5 MiB
512 KiB
524,288 B
4.882812e-4 GiB
4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
15 W
15,000 mW
0.0201 hp
0.015 kW
2.2 GHz
2,200 MHz
2,200,000 kHz
3.4 GHz
3,400 MHz
3,400,000 kHz
3.2 GHz
3,200 MHz
3,200,000 kHz
32 GiB
32,768 MiB
33,554,432 KiB
34,359,738,368 B
0.0313 TiB
Iris Graphics 540300 MHz
0.3 GHz
300,000 KHz
1,050 MHz
1.05 GHz
1,050,000 KHz
✔✔✔✔✔✔
i7-6660U20 March 2016$ 415.00
€ 373.50
£ 336.15
¥ 42,881.95
Core i7Skylake U240.5 MiB
512 KiB
524,288 B
4.882812e-4 GiB
4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
15 W
15,000 mW
0.0201 hp
0.015 kW
2.4 GHz
2,400 MHz
2,400,000 kHz
3.4 GHz
3,400 MHz
3,400,000 kHz
3.4 GHz
3,400 MHz
3,400,000 kHz
32 GiB
32,768 MiB
33,554,432 KiB
34,359,738,368 B
0.0313 TiB
Iris Graphics 540300 MHz
0.3 GHz
300,000 KHz
1,050 MHz
1.05 GHz
1,050,000 KHz
✔✔✔✔✔✔
i7-670027 September 2015$ 312.00
€ 280.80
£ 252.72
¥ 32,238.96
Core i7Skylake S481 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
65 W
65,000 mW
0.0872 hp
0.065 kW
3.4 GHz
3,400 MHz
3,400,000 kHz
4 GHz
4,000 MHz
4,000,000 kHz
3.9 GHz
3,900 MHz
3,900,000 kHz
3.8 GHz
3,800 MHz
3,800,000 kHz
3.7 GHz
3,700 MHz
3,700,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
HD Graphics 530350 MHz
0.35 GHz
350,000 KHz
1,150 MHz
1.15 GHz
1,150,000 KHz
✘✔✔✔✔✘
i7-6700HQ27 September 2015$ 378.00
€ 340.20
£ 306.18
¥ 39,058.74
Core i7Skylake H481 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
6 MiB
6,144 KiB
6,291,456 B
0.00586 GiB
45 W
45,000 mW
0.0603 hp
0.045 kW
2.6 GHz
2,600 MHz
2,600,000 kHz
3.5 GHz
3,500 MHz
3,500,000 kHz
3.3 GHz
3,300 MHz
3,300,000 kHz
3.2 GHz
3,200 MHz
3,200,000 kHz
3.1 GHz
3,100 MHz
3,100,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
HD Graphics 530350 MHz
0.35 GHz
350,000 KHz
1,050 MHz
1.05 GHz
1,050,000 KHz
✔✔✔✘✘✘
i7-6700K27 September 2015$ 350.00
€ 315.00
£ 283.50
¥ 36,165.50
Core i7Skylake S481 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
91 W
91,000 mW
0.122 hp
0.091 kW
4 GHz
4,000 MHz
4,000,000 kHz
4.2 GHz
4,200 MHz
4,200,000 kHz
4 GHz
4,000 MHz
4,000,000 kHz
4 GHz
4,000 MHz
4,000,000 kHz
4 GHz
4,000 MHz
4,000,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
HD Graphics 530350 MHz
0.35 GHz
350,000 KHz
1,150 MHz
1.15 GHz
1,150,000 KHz
✔✔✔✘✔✘
i7-6700T27 September 2015$ 303.00
€ 272.70
£ 245.43
¥ 31,308.99
Core i7Skylake S481 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
35 W
35,000 mW
0.0469 hp
0.035 kW
2.8 GHz
2,800 MHz
2,800,000 kHz
3.6 GHz
3,600 MHz
3,600,000 kHz
3.5 GHz
3,500 MHz
3,500,000 kHz
3.4 GHz
3,400 MHz
3,400,000 kHz
3.4 GHz
3,400 MHz
3,400,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
HD Graphics 530350 MHz
0.35 GHz
350,000 KHz
1,100 MHz
1.1 GHz
1,100,000 KHz
✔✔✔✔✔✔
i7-6700TE19 October 2015$ 303.00
€ 272.70
£ 245.43
¥ 31,308.99
Core i7Skylake S481 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
35 W
35,000 mW
0.0469 hp
0.035 kW
2.4 GHz
2,400 MHz
2,400,000 kHz
3.4 GHz
3,400 MHz
3,400,000 kHz
3.3 GHz
3,300 MHz
3,300,000 kHz
3.2 GHz
3,200 MHz
3,200,000 kHz
3.1 GHz
3,100 MHz
3,100,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
HD Graphics 530350 MHz
0.35 GHz
350,000 KHz
1,000 MHz
1 GHz
1,000,000 KHz
✔✔✔✔✔✔
i7-6770HQ2 January 2016$ 434.00
€ 390.60
£ 351.54
¥ 44,845.22
Core i7Skylake H481 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
6 MiB
6,144 KiB
6,291,456 B
0.00586 GiB
45 W
45,000 mW
0.0603 hp
0.045 kW
2.6 GHz
2,600 MHz
2,600,000 kHz
3.5 GHz
3,500 MHz
3,500,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
Iris Pro Graphics 580350 MHz
0.35 GHz
350,000 KHz
950 MHz
0.95 GHz
950,000 KHz
✔✔✔✘✘✘
i7-6785R22 April 2016$ 370.00
€ 333.00
£ 299.70
¥ 38,232.10
Core i7Skylake H481 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
65 W
65,000 mW
0.0872 hp
0.065 kW
3.3 GHz
3,300 MHz
3,300,000 kHz
3.9 GHz
3,900 MHz
3,900,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
Iris Pro Graphics 580350 MHz
0.35 GHz
350,000 KHz
1,150 MHz
1.15 GHz
1,150,000 KHz
✔✔✔✔✔✘
i7-6820EQ12 October 2015$ 378.00
€ 340.20
£ 306.18
¥ 39,058.74
Core i7Skylake H481 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
45 W
45,000 mW
0.0603 hp
0.045 kW
2.8 GHz
2,800 MHz
2,800,000 kHz
3.5 GHz
3,500 MHz
3,500,000 kHz
3.4 GHz
3,400 MHz
3,400,000 kHz
3.3 GHz
3,300 MHz
3,300,000 kHz
3.2 GHz
3,200 MHz
3,200,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
HD Graphics 530350 MHz
0.35 GHz
350,000 KHz
1,000 MHz
1 GHz
1,000,000 KHz
✔✔✔✔✔✔
i7-6820HK27 September 2015$ 378.00
€ 340.20
£ 306.18
¥ 39,058.74
Core i7Skylake H481 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
45 W
45,000 mW
0.0603 hp
0.045 kW
2.7 GHz
2,700 MHz
2,700,000 kHz
3.6 GHz
3,600 MHz
3,600,000 kHz
3.4 GHz
3,400 MHz
3,400,000 kHz
3.3 GHz
3,300 MHz
3,300,000 kHz
3.2 GHz
3,200 MHz
3,200,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
HD Graphics 530350 MHz
0.35 GHz
350,000 KHz
1,050 MHz
1.05 GHz
1,050,000 KHz
✔✔✔✘✔✘
i7-6820HQ27 October 2015$ 378.00
€ 340.20
£ 306.18
¥ 39,058.74
Core i7Skylake H481 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
45 W
45,000 mW
0.0603 hp
0.045 kW
2.7 GHz
2,700 MHz
2,700,000 kHz
3.6 GHz
3,600 MHz
3,600,000 kHz
3.4 GHz
3,400 MHz
3,400,000 kHz
3.2 GHz
3,200 MHz
3,200,000 kHz
3.2 GHz
3,200 MHz
3,200,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
HD Graphics 530350 MHz
0.35 GHz
350,000 KHz
1,050 MHz
1.05 GHz
1,050,000 KHz
✔✔✔✔✔✔
i7-6822EQ12 October 2015$ 378.00
€ 340.20
£ 306.18
¥ 39,058.74
Core i7Skylake H481 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
25 W
25,000 mW
0.0335 hp
0.025 kW
2 GHz
2,000 MHz
2,000,000 kHz
2.8 GHz
2,800 MHz
2,800,000 kHz
2.7 GHz
2,700 MHz
2,700,000 kHz
2.6 GHz
2,600 MHz
2,600,000 kHz
2.55 GHz
2,550 MHz
2,550,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
HD Graphics 530350 MHz
0.35 GHz
350,000 KHz
1,000 MHz
1 GHz
1,000,000 KHz
✔✔✔✔✔✔
i7-6870HQ2 January 2016$ 434.00
€ 390.60
£ 351.54
¥ 44,845.22
Core i7Skylake H481 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
45 W
45,000 mW
0.0603 hp
0.045 kW
2.7 GHz
2,700 MHz
2,700,000 kHz
3.6 GHz
3,600 MHz
3,600,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
Iris Pro Graphics 580350 MHz
0.35 GHz
350,000 KHz
1,000 MHz
1 GHz
1,000,000 KHz
✔✔✔✘✘✘
i7-6920HQ27 October 2015$ 568.00
€ 511.20
£ 460.08
¥ 58,691.44
Core i7Skylake H481 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
45 W
45,000 mW
0.0603 hp
0.045 kW
2.9 GHz
2,900 MHz
2,900,000 kHz
3.8 GHz
3,800 MHz
3,800,000 kHz
3.6 GHz
3,600 MHz
3,600,000 kHz
3.5 GHz
3,500 MHz
3,500,000 kHz
3.4 GHz
3,400 MHz
3,400,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
HD Graphics 530350 MHz
0.35 GHz
350,000 KHz
1,050 MHz
1.05 GHz
1,050,000 KHz
✔✔✔✔✔✔
i7-6970HQ2 January 2016$ 623.00
€ 560.70
£ 504.63
¥ 64,374.59
Core i7Skylake H481 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
45 W
45,000 mW
0.0603 hp
0.045 kW
2.8 GHz
2,800 MHz
2,800,000 kHz
3.7 GHz
3,700 MHz
3,700,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
Iris Pro Graphics 580350 MHz
0.35 GHz
350,000 KHz
1,050 MHz
1.05 GHz
1,050,000 KHz
✔✔✔✘✘✘
i7-7500U30 August 2016$ 393.00
€ 353.70
£ 318.33
¥ 40,608.69
Core i7Kaby Lake U240.5 MiB
512 KiB
524,288 B
4.882812e-4 GiB
4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
15 W
15,000 mW
0.0201 hp
0.015 kW
2.7 GHz
2,700 MHz
2,700,000 kHz
3.5 GHz
3,500 MHz
3,500,000 kHz
32 GiB
32,768 MiB
33,554,432 KiB
34,359,738,368 B
0.0313 TiB
HD Graphics 620300 MHz
0.3 GHz
300,000 KHz
1,050 MHz
1.05 GHz
1,050,000 KHz
✔✔✔✘✘✘
i7-8565U28 August 2018$ 409.00
€ 368.10
£ 331.29
¥ 42,261.97
Core i7Whiskey Lake U481 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
15 W
15,000 mW
0.0201 hp
0.015 kW
1.8 GHz
1,800 MHz
1,800,000 kHz
4.6 GHz
4,600 MHz
4,600,000 kHz
4.5 GHz
4,500 MHz
4,500,000 kHz
4.1 GHz
4,100 MHz
4,100,000 kHz
32 GiB
32,768 MiB
33,554,432 KiB
34,359,738,368 B
0.0313 TiB
UHD Graphics 620300 MHz
0.3 GHz
300,000 KHz
1,150 MHz
1.15 GHz
1,150,000 KHz
✔✔✔✘✘✘
m3-6Y3027 September 2015$ 281.00
€ 252.90
£ 227.61
¥ 29,035.73
Core m3Skylake Y240.5 MiB
512 KiB
524,288 B
4.882812e-4 GiB
4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
4.5 W
4,500 mW
0.00603 hp
0.0045 kW
0.9 GHz
900 MHz
900,000 kHz
2.2 GHz
2,200 MHz
2,200,000 kHz
2 GHz
2,000 MHz
2,000,000 kHz
16 GiB
16,384 MiB
16,777,216 KiB
17,179,869,184 B
0.0156 TiB
HD Graphics 515300 MHz
0.3 GHz
300,000 KHz
850 MHz
0.85 GHz
850,000 KHz
✔✔✔✘✘✘
m5-6Y5427 September 2015$ 281.00
€ 252.90
£ 227.61
¥ 29,035.73
Core m5Skylake Y240.5 MiB
512 KiB
524,288 B
4.882812e-4 GiB
4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
4.5 W
4,500 mW
0.00603 hp
0.0045 kW
1.1 GHz
1,100 MHz
1,100,000 kHz
2.7 GHz
2,700 MHz
2,700,000 kHz
2.4 GHz
2,400 MHz
2,400,000 kHz
16 GiB
16,384 MiB
16,777,216 KiB
17,179,869,184 B
0.0156 TiB
HD Graphics 515300 MHz
0.3 GHz
300,000 KHz
900 MHz
0.9 GHz
900,000 KHz
✔✔✔✘✘✘
m5-6Y5727 September 2015$ 281.00
€ 252.90
£ 227.61
¥ 29,035.73
Core m5Skylake Y240.5 MiB
512 KiB
524,288 B
4.882812e-4 GiB
4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
4.5 W
4,500 mW
0.00603 hp
0.0045 kW
1.1 GHz
1,100 MHz
1,100,000 kHz
2.8 GHz
2,800 MHz
2,800,000 kHz
2.4 GHz
2,400 MHz
2,400,000 kHz
16 GiB
16,384 MiB
16,777,216 KiB
17,179,869,184 B
0.0156 TiB
HD Graphics 515300 MHz
0.3 GHz
300,000 KHz
900 MHz
0.9 GHz
900,000 KHz
✔✔✔✔✔✔
m7-6Y7527 September 2015$ 393.00
€ 353.70
£ 318.33
¥ 40,608.69
Core m7Skylake Y240.5 MiB
512 KiB
524,288 B
4.882812e-4 GiB
4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
4.5 W
4,500 mW
0.00603 hp
0.0045 kW
1.2 GHz
1,200 MHz
1,200,000 kHz
3.1 GHz
3,100 MHz
3,100,000 kHz
2.9 GHz
2,900 MHz
2,900,000 kHz
16 GiB
16,384 MiB
16,777,216 KiB
17,179,869,184 B
0.0156 TiB
HD Graphics 515300 MHz
0.3 GHz
300,000 KHz
1,000 MHz
1 GHz
1,000,000 KHz
✔✔✔✔✔✔
4405U3 November 2015$ 161.00
€ 144.90
£ 130.41
¥ 16,636.13
PentiumSkylake U240.5 MiB
512 KiB
524,288 B
4.882812e-4 GiB
2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
15 W
15,000 mW
0.0201 hp
0.015 kW
2.1 GHz
2,100 MHz
2,100,000 kHz
32 GiB
32,768 MiB
33,554,432 KiB
34,359,738,368 B
0.0313 TiB
HD Graphics 510300 MHz
0.3 GHz
300,000 KHz
950 MHz
0.95 GHz
950,000 KHz
✘✔✘✘✘✘
4405Y3 November 2015$ 161.00
€ 144.90
£ 130.41
¥ 16,636.13
PentiumSkylake Y240.5 MiB
512 KiB
524,288 B
4.882812e-4 GiB
2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
6 W
6,000 mW
0.00805 hp
0.006 kW
1.5 GHz
1,500 MHz
1,500,000 kHz
16 GiB
16,384 MiB
16,777,216 KiB
17,179,869,184 B
0.0156 TiB
HD Graphics 515300 MHz
0.3 GHz
300,000 KHz
800 MHz
0.8 GHz
800,000 KHz
✘✔✘✘✘✘
G440027 September 2015$ 64.00
€ 57.60
£ 51.84
¥ 6,613.12
PentiumSkylake S220.5 MiB
512 KiB
524,288 B
4.882812e-4 GiB
3 MiB
3,072 KiB
3,145,728 B
0.00293 GiB
54 W
54,000 mW
0.0724 hp
0.054 kW
3.3 GHz
3,300 MHz
3,300,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
HD Graphics 510350 MHz
0.35 GHz
350,000 KHz
1,000 MHz
1 GHz
1,000,000 KHz
✘✘✔✘✘✘
G4400T27 September 2015$ 64.00
€ 57.60
£ 51.84
¥ 6,613.12
PentiumSkylake S220.5 MiB
512 KiB
524,288 B
4.882812e-4 GiB
3 MiB
3,072 KiB
3,145,728 B
0.00293 GiB
35 W
35,000 mW
0.0469 hp
0.035 kW
2.9 GHz
2,900 MHz
2,900,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
HD Graphics 510350 MHz
0.35 GHz
350,000 KHz
950 MHz
0.95 GHz
950,000 KHz
✘✘✔✘✘✘
G4400TE9 December 2015$ 64.00
€ 57.60
£ 51.84
¥ 6,613.12
PentiumSkylake S220.5 MiB
512 KiB
524,288 B
4.882812e-4 GiB
3 MiB
3,072 KiB
3,145,728 B
0.00293 GiB
35 W
35,000 mW
0.0469 hp
0.035 kW
2.4 GHz
2,400 MHz
2,400,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
HD Graphics 510350 MHz
0.35 GHz
350,000 KHz
950 MHz
0.95 GHz
950,000 KHz
✘✘✔✘✘✘
G450027 September 2015$ 82.00
€ 73.80
£ 66.42
¥ 8,473.06
PentiumSkylake S220.5 MiB
512 KiB
524,288 B
4.882812e-4 GiB
3 MiB
3,072 KiB
3,145,728 B
0.00293 GiB
51 W
51,000 mW
0.0684 hp
0.051 kW
3.5 GHz
3,500 MHz
3,500,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
HD Graphics 530350 MHz
0.35 GHz
350,000 KHz
1,050 MHz
1.05 GHz
1,050,000 KHz
✘✘✔✘✘✘
G4500T27 September 2015$ 75.00
€ 67.50
£ 60.75
¥ 7,749.75
PentiumSkylake S220.5 MiB
512 KiB
524,288 B
4.882812e-4 GiB
3 MiB
3,072 KiB
3,145,728 B
0.00293 GiB
35 W
35,000 mW
0.0469 hp
0.035 kW
3 GHz
3,000 MHz
3,000,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
HD Graphics 530350 MHz
0.35 GHz
350,000 KHz
950 MHz
0.95 GHz
950,000 KHz
✘✘✔✘✘✘
G452027 September 2015$ 93.00
€ 83.70
£ 75.33
¥ 9,609.69
PentiumSkylake S220.5 MiB
512 KiB
524,288 B
4.882812e-4 GiB
3 MiB
3,072 KiB
3,145,728 B
0.00293 GiB
51 W
51,000 mW
0.0684 hp
0.051 kW
3.6 GHz
3,600 MHz
3,600,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
HD Graphics 530350 MHz
0.35 GHz
350,000 KHz
1,050 MHz
1.05 GHz
1,050,000 KHz
✘✘✔✘✘✘
E3-1220 v519 October 2015$ 203.00
€ 182.70
£ 164.43
¥ 20,975.99
Xeon E3Skylake DT441 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
80 W
80,000 mW
0.107 hp
0.08 kW
3 GHz
3,000 MHz
3,000,000 kHz
3.5 GHz
3,500 MHz
3,500,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
✔✘✔✔✔✔
E3-1225 v519 October 2015$ 224.00
€ 201.60
£ 181.44
¥ 23,145.92
Xeon E3Skylake DT441 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
80 W
80,000 mW
0.107 hp
0.08 kW
3.3 GHz
3,300 MHz
3,300,000 kHz
3.7 GHz
3,700 MHz
3,700,000 kHz
3.6 GHz
3,600 MHz
3,600,000 kHz
3.5 GHz
3,500 MHz
3,500,000 kHz
3.4 GHz
3,400 MHz
3,400,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
HD Graphics P530400 MHz
0.4 GHz
400,000 KHz
1,150 MHz
1.15 GHz
1,150,000 KHz
✔✘✔✔✔✔
E3-1235L v519 October 2015$ 250.00
€ 225.00
£ 202.50
¥ 25,832.50
Xeon E3Skylake DT441 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
25 W
25,000 mW
0.0335 hp
0.025 kW
2 GHz
2,000 MHz
2,000,000 kHz
3 GHz
3,000 MHz
3,000,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
HD Graphics P530400 MHz
0.4 GHz
400,000 KHz
1,150 MHz
1.15 GHz
1,150,000 KHz
✔✘✔✔✔✔
E3-1240 v519 October 2015$ 282.00
€ 253.80
£ 228.42
¥ 29,139.06
Xeon E3Skylake DT481 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
80 W
80,000 mW
0.107 hp
0.08 kW
3.5 GHz
3,500 MHz
3,500,000 kHz
3.9 GHz
3,900 MHz
3,900,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
✔✔✔✔✔✔
E3-1240L v519 October 2015$ 278.00
€ 250.20
£ 225.18
¥ 28,725.74
Xeon E3Skylake DT481 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
25 W
25,000 mW
0.0335 hp
0.025 kW
2.1 GHz
2,100 MHz
2,100,000 kHz
3.2 GHz
3,200 MHz
3,200,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
✔✔✔✔✔✔
E3-1245 v519 October 2015$ 294.00
€ 264.60
£ 238.14
¥ 30,379.02
Xeon E3Skylake DT481 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
80 W
80,000 mW
0.107 hp
0.08 kW
3.5 GHz
3,500 MHz
3,500,000 kHz
3.9 GHz
3,900 MHz
3,900,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
HD Graphics P530400 MHz
0.4 GHz
400,000 KHz
1,150 MHz
1.15 GHz
1,150,000 KHz
✔✔✔✔✔✔
E3-1260L v519 October 2015$ 294.00
€ 264.60
£ 238.14
¥ 30,379.02
Xeon E3Skylake DT481 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
45 W
45,000 mW
0.0603 hp
0.045 kW
2.9 GHz
2,900 MHz
2,900,000 kHz
3.9 GHz
3,900 MHz
3,900,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
✔✔✔✔✔✔
E3-1268L v519 October 2015$ 377.00
€ 339.30
£ 305.37
¥ 38,955.41
Xeon E3Skylake DT481 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
35 W
35,000 mW
0.0469 hp
0.035 kW
2.4 GHz
2,400 MHz
2,400,000 kHz
3.4 GHz
3,400 MHz
3,400,000 kHz
3.3 GHz
3,300 MHz
3,300,000 kHz
3.2 GHz
3,200 MHz
3,200,000 kHz
3.1 GHz
3,100 MHz
3,100,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
HD Graphics P530350 MHz
0.35 GHz
350,000 KHz
1,000 MHz
1 GHz
1,000,000 KHz
✔✔✔✔✔✔
E3-1270 v519 October 2015$ 339.00
€ 305.10
£ 274.59
¥ 35,028.87
Xeon E3Skylake DT481 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
80 W
80,000 mW
0.107 hp
0.08 kW
3.6 GHz
3,600 MHz
3,600,000 kHz
4 GHz
4,000 MHz
4,000,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
✔✔✔✔✔✔
E3-1275 v519 October 2015$ 350.00
€ 315.00
£ 283.50
¥ 36,165.50
Xeon E3Skylake DT481 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
80 W
80,000 mW
0.107 hp
0.08 kW
3.6 GHz
3,600 MHz
3,600,000 kHz
4 GHz
4,000 MHz
4,000,000 kHz
3.9 GHz
3,900 MHz
3,900,000 kHz
3.8 GHz
3,800 MHz
3,800,000 kHz
3.7 GHz
3,700 MHz
3,700,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
HD Graphics P530400 MHz
0.4 GHz
400,000 KHz
1,150 MHz
1.15 GHz
1,150,000 KHz
✔✔✔✔✔✔
E3-1280 v519 October 2015$ 612.00
€ 550.80
£ 495.72
¥ 63,237.96
Xeon E3Skylake DT481 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
80 W
80,000 mW
0.107 hp
0.08 kW
3.7 GHz
3,700 MHz
3,700,000 kHz
4 GHz
4,000 MHz
4,000,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
✔✔✔✔✔✔
E3-1505L v512 October 2015$ 433.00
€ 389.70
£ 350.73
¥ 44,741.89
Xeon E3Skylake H481 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
25 W
25,000 mW
0.0335 hp
0.025 kW
2 GHz
2,000 MHz
2,000,000 kHz
2.8 GHz
2,800 MHz
2,800,000 kHz
2.7 GHz
2,700 MHz
2,700,000 kHz
2.6 GHz
2,600 MHz
2,600,000 kHz
2.55 GHz
2,550 MHz
2,550,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
HD Graphics P530350 MHz
0.35 GHz
350,000 KHz
1,000 MHz
1 GHz
1,000,000 KHz
✔✔✔✔✔✔
E3-1505M v512 October 2015$ 434.00
€ 390.60
£ 351.54
¥ 44,845.22
Xeon E3Skylake H481 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
45 W
45,000 mW
0.0603 hp
0.045 kW
2.8 GHz
2,800 MHz
2,800,000 kHz
3.7 GHz
3,700 MHz
3,700,000 kHz
3.5 GHz
3,500 MHz
3,500,000 kHz
3.4 GHz
3,400 MHz
3,400,000 kHz
3.3 GHz
3,300 MHz
3,300,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
HD Graphics P530350 MHz
0.35 GHz
350,000 KHz
1,050 MHz
1.05 GHz
1,050,000 KHz
✔✔✔✘✔✔
E3-1515M v52 January 2016$ 489.00
€ 440.10
£ 396.09
¥ 50,528.37
Xeon E3Skylake H481 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
45 W
45,000 mW
0.0603 hp
0.045 kW
2.8 GHz
2,800 MHz
2,800,000 kHz
3.7 GHz
3,700 MHz
3,700,000 kHz
3.6 GHz
3,600 MHz
3,600,000 kHz
3.5 GHz
3,500 MHz
3,500,000 kHz
3.3 GHz
3,300 MHz
3,300,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
Iris Pro Graphics P580350 MHz
0.35 GHz
350,000 KHz
1,000 MHz
1 GHz
1,000,000 KHz
✔✔✔✔✔✔
E3-1535M V512 October 2015$ 623.00
€ 560.70
£ 504.63
¥ 64,374.59
Xeon E3Skylake H481 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
45 W
45,000 mW
0.0603 hp
0.045 kW
2.9 GHz
2,900 MHz
2,900,000 kHz
3.8 GHz
3,800 MHz
3,800,000 kHz
3.6 GHz
3,600 MHz
3,600,000 kHz
3.5 GHz
3,500 MHz
3,500,000 kHz
3.4 GHz
3,400 MHz
3,400,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
HD Graphics P530350 MHz
0.35 GHz
350,000 KHz
1,050 MHz
1.05 GHz
1,050,000 KHz
✔✔✔✔✔✔
E3-1545M v52 January 2016$ 679.00
€ 611.10
£ 549.99
¥ 70,161.07
Xeon E3Skylake H481 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
45 W
45,000 mW
0.0603 hp
0.045 kW
2.9 GHz
2,900 MHz
2,900,000 kHz
3.8 GHz
3,800 MHz
3,800,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
Iris Pro Graphics P580350 MHz
0.35 GHz
350,000 KHz
1,050 MHz
1.05 GHz
1,050,000 KHz
✔✔✔✔✔✔
E3-1558L v531 May 2016$ 396.00
€ 356.40
£ 320.76
¥ 40,918.68
Xeon E3Skylake H481 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
45 W
45,000 mW
0.0603 hp
0.045 kW
1.9 GHz
1,900 MHz
1,900,000 kHz
3.3 GHz
3,300 MHz
3,300,000 kHz
3.2 GHz
3,200 MHz
3,200,000 kHz
3.1 GHz
3,100 MHz
3,100,000 kHz
3.1 GHz
3,100 MHz
3,100,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
Iris Pro Graphics P555650 MHz
0.65 GHz
650,000 KHz
1,000 MHz
1 GHz
1,000,000 KHz
✔✔✔✔✔✔
E3-1565L v531 May 2016$ 417.00
€ 375.30
£ 337.77
¥ 43,088.61
Xeon E3Skylake H481 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
35 W
35,000 mW
0.0469 hp
0.035 kW
2.5 GHz
2,500 MHz
2,500,000 kHz
3.5 GHz
3,500 MHz
3,500,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
Iris Pro Graphics P580350 MHz
0.35 GHz
350,000 KHz
1,050 MHz
1.05 GHz
1,050,000 KHz
✔✔✔✔✔✔
E3-1575M v52 January 2016$ 1,207.00
€ 1,086.30
£ 977.67
¥ 124,719.31
Xeon E3Skylake H481 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
45 W
45,000 mW
0.0603 hp
0.045 kW
3 GHz
3,000 MHz
3,000,000 kHz
3.9 GHz
3,900 MHz
3,900,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
Iris Pro Graphics P580350 MHz
0.35 GHz
350,000 KHz
1,100 MHz
1.1 GHz
1,100,000 KHz
✔✔✔✔✔✔
E3-1578L v531 May 2016$ 449.00
€ 404.10
£ 363.69
¥ 46,395.17
Xeon E3Skylake H481 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
45 W
45,000 mW
0.0603 hp
0.045 kW
2 GHz
2,000 MHz
2,000,000 kHz
3.4 GHz
3,400 MHz
3,400,000 kHz
3.3 GHz
3,300 MHz
3,300,000 kHz
3.2 GHz
3,200 MHz
3,200,000 kHz
3.2 GHz
3,200 MHz
3,200,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
Iris Pro Graphics P580350 MHz
0.35 GHz
350,000 KHz
1,000 MHz
1 GHz
1,000,000 KHz
✔✔✔✔✔✔
E3-1585 v531 May 2016$ 556.00
€ 500.40
£ 450.36
¥ 57,451.48
Xeon E3Skylake H481 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
65 W
65,000 mW
0.0872 hp
0.065 kW
3.5 GHz
3,500 MHz
3,500,000 kHz
3.9 GHz
3,900 MHz
3,900,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
Iris Pro Graphics P580350 MHz
0.35 GHz
350,000 KHz
1,150 MHz
1.15 GHz
1,150,000 KHz
✔✔✔✔✔✔
E3-1585L v531 May 2016$ 445.00
€ 400.50
£ 360.45
¥ 45,981.85
Xeon E3Skylake H481 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
45 W
45,000 mW
0.0603 hp
0.045 kW
3 GHz
3,000 MHz
3,000,000 kHz
3.7 GHz
3,700 MHz
3,700,000 kHz
64 GiB
65,536 MiB
67,108,864 KiB
68,719,476,736 B
0.0625 TiB
Iris Pro Graphics P580350 MHz
0.35 GHz
350,000 KHz
1,150 MHz
1.15 GHz
1,150,000 KHz
✔✔✔✔✔✔
 Multiprocessors (2-way)
 Multiprocessors (4-way)
 Multiprocessors (8-way)
Count: 105

References

  • 2014 Intel Developer Forum in San Francisco, September 9, 2014
  • Julius Mandelblat, Senior Principal Engineer, Lead Architect, 2015 IDF in San Francisco, Session SPCS001 ("Technology Insight: Intel’s Next Generation Microarchitecture Code Name Skylake"), August 18, 2015
  • Efraim Rotem, Senior Principal Engineer, Lead Client Power Architect, 2015 IDF in San Francisco, Session ARCS001 ("Intel® Architecture, Code Name Skylake Deep Dive: A New Architecture to Manage Power Performance and Energy Efficiency"), August 18, 2015
  • David Blythe, Intel Fellow and Chief Graphics Software Architect, 2015 IDF in San Francisco, Session SPCS003 ("Technology Insight: Next Generation Intel® Processor Graphics Architecture, Code Name Skylake"), August 18, 2015
  • Dan Ragland, Overclocking System Architect, 2015 IDF, in San Francisco, Session RPCS001 ("Overclocking 6th Generation Intel® Core™ Processors!"), August 18, 2015
  • Jack Doweck, Intel, Hot Chips 28, 2016
  • Fayneh, Eyal, et al. "4.1 14nm 6th-generation Core processor SoC with low power consumption and improved performance." Solid-State Circuits Conference (ISSCC), 2016 IEEE International. IEEE, 2016.

Documents


See also

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/microarchitectures/skylake_(client)&oldid=55597"
Facts about "Skylake (client) - Microarchitectures - Intel"
RDF feed
codenameSkylake +
core count2 +, 4 +, 6 +, 8 +, 10 +, 12 +, 14 +, 16 +, 18 +, 20 +, 22 +, 24 +, 26 + and 28 +
designerIntel +
first launchedAugust 5, 2015 +
full page nameintel/microarchitectures/skylake (client) +
instance ofmicroarchitecture +
instruction set architecturex86-16 +, x86-32 + and x86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameSkylake +
pipeline stages (max)19 +
pipeline stages (min)14 +
process14 nm (0.014 μm, 1.4e-5 mm) +